Latched accumulator fractional N synthesis with residual error r

Details Latched accumulator fractional N synthesis with residual error r Latched accumulator fractional N synthesis with residual error r

1990-08-31

1992-03-03

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 16, 331 25, 332127, 375120, 377 48, 455 76, 455183, 455260, H03C 309, H03L 7197

Patent

active

050936328

ABSTRACT:
A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).

REFERENCES:
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patent: 4816774 (1989-03-01), Martin
Brewerton et al., "Defining the Elements of Good Design", Microwaves and RF, Jun. 1984, pp. 79-85, 124.

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