Latch with data jitter free clock load

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

Reexamination Certificate

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Details

C327S201000, C327S211000, C327S212000, C327S218000

Reexamination Certificate

active

07023255

ABSTRACT:
A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. The latch circuit has a second load value relative to a clock driver when data at the first and second data inputs is changing. The digital latch further includes a load compensation circuit operatively connected to the first and second data inputs of the latch circuit and to the first and second data outputs of the latch circuit. The load compensation circuit provides a first compensation load value upon the clock driver when data at the first and second data inputs is non-changing and provides a second compensation load value relative upon the clock driver when data at the first and second data inputs is changing such that a sum of the first load value and the first compensation load value equals a sum of the second load value and the second compensation load value.

REFERENCES:
patent: 5689257 (1997-11-01), Mercer et al.
patent: 6031477 (2000-02-01), Mercer
patent: 6344816 (2002-02-01), Dedic
patent: 6366113 (2002-04-01), Song
patent: 6734816 (2004-05-01), Morimoto et al.
patent: 2004/0140931 (2004-07-01), Vesuna
“Sense Amplifier-Based Flip-Flop,” Nikolic et al.IEEE International Solid-State Circuits Conference. 1999.

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