Latch-up restistant ESD protection circuit and method thereof

Details Latch-up restistant ESD protection circuit and method thereof Latch-up restistant ESD protection circuit and method thereof

2007-02-15

2008-07-22

Sherry, Michael J (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S091100, C361S111000, C361S118000

Reexamination Certificate

active

07403362

ABSTRACT:
The present invention is to provide a latch-up resistant electrostatic discharge (ESD) protection circuit and method thereof, which comprises a clamping circuit being able to discharge when activated, a sustaining unit for directing electrostatic charge via said sustaining unit to said clamping circuit when activated and a sensing unit for activating said clamping circuit and said sustaining unit. When an ESD event, a signal noise or a power bounce is detected, said clamping circuit and said sensing unit is activated, said sustaining unit is activated to increase discharging ability of said clamping circuit, and then said sensing unit self resets after a period of time to deactivate said sustaining unit, thereby said clamping circuit is deactivated and a latch-up is prevented.

REFERENCES:
patent: 5910873 (1999-06-01), Boluna et al.
patent: 5946177 (1999-08-01), Miller et al.
patent: 6665160 (2003-12-01), Lin et al.
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patent: 7050282 (2006-05-01), Chuang et al.
patent: 2003/0026054 (2003-02-01), Hulfachor et al.
patent: 2003/0223166 (2003-12-01), Chen et al.
patent: 2005/0002139 (2005-01-01), Yeh et al.
patent: 2007/0171587 (2007-07-01), Lee et al.

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