Latch-up resistant CMOS structure for VLSI including retrograded

Details Latch-up resistant CMOS structure for VLSI including retrograded Latch-up resistant CMOS structure for VLSI including retrograded

1986-02-28

1987-07-28

Clawson, Jr., Joseph E.

357 2311, 357 38, 357 52, 357 56, 357 90, H01L 2702

Patent

active

046834885

ABSTRACT:
A complementary metal oxide semiconductor (CMOS) structure having the source and drain regions of individual transistor devices separated from the peak impurity concentrations of the respective N- and P-wells of such devices. The CMOS structure includes trenches between the individual transistor devices, and highly doped field regions are formed in the bottom of the trenches. Each N- and P-well includes a retrograde impurity concentration profile and extends beneath adjacent trenches.

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