Latch-up resistant CMOS process

Details Latch-up resistant CMOS process Latch-up resistant CMOS process

1989-10-25

1991-09-17

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 62, 437 34, 437 78, 437 68, H01L 21336

Patent

active

050495194

ABSTRACT:
A latch-up free CMOS structure and method of fabrication thereof is disclosed. A P-type substrate (40) is appropriately masked to form a plurality of sites in which isolated wells (50) are formed. A thermal oxide layer (56) is grown on the surface of each well (50), and a boron channel stop (62) implanted therearound. Polysilicon semiconductor material (68) is formed within each well, and implant doped to form an N-well (76) of material. The P-substrate (40) is planarized. PMOS transistors are formed within the oxide isolate N-wells (76), while NMOS transistors are formed in the P-substrate (40) outside the wells.

REFERENCES:
patent: 4075754 (1978-02-01), Cook, Jr.
patent: 4299024 (1981-11-01), Piotrowski
patent: 4416050 (1983-01-01), Sarace
patent: 4507158 (1985-03-01), Kamins et al.
patent: 4570330 (1986-02-01), Cogan
patent: 4593458 (1986-06-01), Adler
patent: 4685199 (1987-08-01), Jastrzebski
patent: 4814287 (1989-03-01), Takemoto et al.
patent: 4879585 (1989-11-01), Usami
Sabine, K. A. et al., IEEE Electron Device Letters, vol. EDL-6, No. 1, Jan. 1985, pp. 43-46.
Kamins, T. I., et al., IEEE Electron Device Letters, vol. EDL-6, No. 12, Dec. 1985, pp. 617-619.
Ghandhi, S. K., VLSI Fabrication Principles, John Wiley, 1983, pp. 358-362, 432-435, 476-500.

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