Latch-up resistant CMOS output circuit

Details Latch-up resistant CMOS output circuit Latch-up resistant CMOS output circuit

1993-05-18

1994-08-16

Callahan, Timothy P.

Electrical transmission or interconnection systems

Personnel safety or limit control features

Interlock

307303, 257372, 257373, H01L 2702

Patent

active

053389867

ABSTRACT:
A CMOS output circuit including a pMOS transistor and an nMOS transistor connected in series between a power supply voltage and a ground voltage, is formed with a resistive component for reducing occurrence of latch-up. The resistive component is arranged at least one of the sources of the pMOS and nMOS transistors so as to be connected in series with a parasitic bipolar transistor formed between the power supply voltage and the ground voltage through its emitter. The resistive component limits the collector current of the parasitic bipolar transistor at a time that a triggering voltage is applied to an output terminal of the output circuit, so that the parasitic bipolar transistor does not turn on readily, thereby resulting in reduced possibility of occurrence of latch-up.

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patent: 5105256 (1992-04-01), Koshimaru
patent: 5146113 (1992-09-01), Okada
patent: 5237195 (1993-08-01), Sadamatsu

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