Latch-up protection circuit for integrated circuits using comple

Details Latch-up protection circuit for integrated circuits using comple Latch-up protection circuit for integrated circuits using comple

1987-03-13

1988-12-13

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200B, 307362, 357 42, 361 86, H03K 1716

Patent

active

047913177

ABSTRACT:
A latch-up protection circuit for an integrated circuit using complementary MOS circuit technology has a substrate bias generator that applies a negative substrate bias to a semiconductor substrate having a p-conductive material into which a well-shaped semiconductor zone of n-conductive material is inserted. In order to avoid latch-up effects in the integrated circuit, an electronic protection circuit interrupts the capacitive charging currents of a capacitor in the substrate depending on the potential of the semiconductor substrate which is taken at a doped substrate bias terminal. The electronic protection circuit connects a capacitor bias generator to the capacitor when a voltage on the substrate bias terminal is less than a sum of a reference potential and a threshold voltage of a first transistor in the electronic protection circuit. The electronic protection circuit disconnects the capacitive bias generator from the capacitor when a voltage on the substrate bias terminal is greater than the sum. During normal operation the electronic protection circuit does not load a supply voltage source or a substrate bias voltage source with current.

REFERENCES:
patent: 4473758 (1984-09-01), Humtington
patent: 4571505 (1986-02-01), Eaton, Jr.
patent: 4670668 (1987-06-01), Liu
patent: 4683488 (1987-07-01), Lee et al.
patent: 4689653 (1987-08-01), Miyazaki
patent: 4701777 (1987-10-01), Takayama et al.
Halbleiter Elektronik, 14, H. Weiss, K. Horninger, "Integrierte MOS-Schaltungen", pp. 247-248.
Static and Transient Latch-Up Hardness in N-well CMOS with ON-Chip Substrate Bias Generator, IEDM 85, "Technical Digest", pp. 504-508.
"CMOS Semiconductor Structure Without Latch-Up and Method of Fabrication", IBM TDB, vol. 27, No. 12, 5-1985, pp. 6968-70.

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