Latch-up protection circuit for integrated circuits biased...

Details Latch-up protection circuit for integrated circuits biased... Latch-up protection circuit for integrated circuits biased...

2000-04-11

2002-10-29

Leja, Ronald W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific voltage responsive fault sensor

C361S086000, C327S543000

Reexamination Certificate

active

06473282

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit technologies. More particularly, the present invention relates to a latch-up protection circuit for integrated circuits biased with multiple power supplies and its method.
2. Description of the Related Art
Due to the different voltage requirements of different integrated circuit (IC) generations, an IC chip may be powered by multiple power supplies at different voltage levels. For example, the IC chip may have input/output circuitry powered by a voltage source of 5V while employing another voltage source of 3.3V to drive internal circuitry, such as memory cells and sense amplifiers.
As shown in
FIG. 1
, a conventional CMOS circuit of an a IC chip with multiple power supplies is schematically illustrated in a cross-sectional view. In the drawing, the CMOS circuitry, formed in a semiconductor substrate
5
, includes high-voltage CMOS circuit block
1
and a low-voltage CMOS circuit block
2
. For example, the CMOS circuitry is implemented by means of a twin-well process; therefore, an n-well
10
and a p-well
11
are provided within the extent of the high-voltage CMOS circuit block
1
, while an n-well
20
and a p-well
21
are provided within the extent of the low-voltage CMOS circuit block
2
. If the semiconductor substrate
5
is a p-type substrate, the p-wells
11
and
21
can be optionally omitted. If the semiconductor substrate
5
is an n-type substrate, the n-wells
10
and
20
can be optionally omitted.
The high-voltage CMOS circuit block
1
is composed of a pMOS transistor and an nMOS transistor. The pMOS transistor includes two spaced-apart p
+
-type diffusion regions
12
and
13
as its source and drain, respectively, and a gate
14
overlying a portion of the n-type well
10
therebetween. The nMOS transistor includes two spaced-apart n
+
-type diffusion regions
15
and
16
as its source and drain, respectively, and a gate
17
overlying a portion of the p-well
11
therebetween. In
FIG. 1
, the high-voltage CMOS circuit block
1
is powered by a higher voltage V
DDH
. Therefore, the pMOS transistor is configured with the p
+
-type source diffusion region
12
connected to a V
DDH
power rail, while the nMOS transistor is configured with the n
+
-type source diffusion region
15
connected to a V
SS
power rail, the V
SS
power rail being connected to the ground potential GND, typically.
Also, the low-voltage CMOS circuit block
2
is composed of a pMOS transistor and an nMOS transistor. The pMOS transistor includes two spaced-apart p
+
-type diffusion regions
22
and
23
as its source and drain, respectively, and a gate
24
overlying a portion of the n-type well
20
therebetween. The nMOS transistor includes two spaced-apart n
+
-type diffusion regions
25
and
26
as its source and drain, respectively, and a gate
27
overlying a portion of the p-well
21
therebetween. In
FIG. 1
, the low-voltage CMOS circuit block
2
is powered by a lower voltage V
DDL
. Therefore, the pMOS transistor is configured with the p
+
-type source diffusion region
22
connected to a V
DDL
power rail, while the nMOS transistor is configured with the n
+
-type source diffusion region
25
connected to the V
SS
power rail, the V
SS
power being connected to the ground potential GND, typically.
Typically, the n-type well
20
is biased via the V
DDH
power rail. As shown in
FIG. 1
, the n-type well
20
is electrically connected to the V
DDH
power rail by an n
+
-type contact region
28
to ensure that the junction between the p
+
-type source diffusion region
22
and the n-type well
20
keeps reverse-biased without causing leakage current. Moreover, the n-well
10
is electrically connected to V
DDH
power rail by an n
−
-type contact region
18
, wherein the p-wells
11
and
21
are electrically connected to the V
SS
power rail by p
+
-type contact regions
19
and
29
, respectively.
However, in a CMOS circuit with multiple power supplies, those power supplies may reach their full levels at different times after the IC chip is powered on. In a non-desirable power-on sequence, the power supply V
DDL
is established at the V
DDL
power rail sooner than the power supply V
DDH
at the V
DDH
power rail. Thus, as shown in
FIG. 2
, a time interval T exists in which the potential of the V
DDL
power rail is temporarily greater than that of the V
DDH
power rail. Under these circumstances, the junction between the p
+
-type diffusion region
22
and the n-type well
20
is momentarily forward biased. Therefore, large current is conducted to flow through the n-type well
20
toward the n
+
-type contact region
28
so that a lateral semiconductor controlled rectifier, comprises the p
+
-type source diffusion region
22
, the n-type well
20
, the p-well
21
, and the n
+
-type source diffusion region
25
, may be triggered to latch-up.
To prevent this, the conventional approach employs a guard ring around the CMOS circuit to collect additional carriers and thus suppress latch-up. However, as there a number of the CMOS circuits biased with multiple power supplies to be integrated in the IC chip, the fact that each CMOS circuit should be enclosed by the associated guard ring takes up a great amount of precious chip area.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a latch-up protection circuit for integrated circuits biased with multiple power supplies to avoid latch-up damage during a non-desirable power-on sequence.
For achieving the aforementioned object, the present invention provides a latch-up protection circuit for an integrated circuit powered through a first power rail and a second power rail, the integrated circuit having at least one semiconductor bulk of a conductivity type. The latch-up protection circuit comprises a control circuit and a switch circuit. The control circuit is connected to the first power rail and the second power rail for detecting a relative voltage therebetween and generating a first control signal and a second control signal. The switch circuit is connected to the first power rail and the control circuit. When the relative voltage is greater than a first predetermined value, the switch circuit in response to the first control signal electrically connects the first power rail with the at least one semiconductor bulk. When the relative voltage is smaller than the first predetermined value, the switch in response to the first control signal electrically disconnects the first power rail from the at least one semiconductor bulk.
Accordingly, the latch-up protection circuit of the present invention can ensure that no forward-bias path exists between the n-well at the low-voltage CMOS circuit and the p
30
-type source diffusion region during any power-on sequence, thus protecting the CMOS integrated circuit from latch-up.


REFERENCES:
patent: 4871927 (1989-10-01), Dallavalle
patent: 5708549 (1998-01-01), Croft
patent: 5742465 (1998-04-01), Yu
patent: 5942932 (1999-08-01), Shen
patent: 6008688 (1999-12-01), Faue
patent: 6014053 (2000-01-01), Womack
patent: 6157070 (2000-12-01), Lin et al.
patent: 6252452 (2001-05-01), Hatori et al.

Affiliated with

Also associated with

Rating

Latch-up protection circuit for integrated circuits biased... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latch-up protection circuit for integrated circuits biased..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latch-up protection circuit for integrated circuits biased... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2920512