Latch-up prevention in a two-power-supply CMOS integrated circui

Details Latch-up prevention in a two-power-supply CMOS integrated circui Latch-up prevention in a two-power-supply CMOS integrated circui

1988-02-23

1989-10-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072962, 307570, H03K 301

Patent

active

048719277

ABSTRACT:
Latch-up in two supplies (+VCC and -VBB) CMOS integrated circuits is prevented by means of a single integrated protection MOS transistor, N-channel for P-Well CMOS or P-channel for N-Well CMOS, having its drain (source) connected to ground and its body region, gate and source (drain) connected to -VBB (+VCC). The desired threshold voltage and dimensions of the protection transistor do not present particular problems of implementation.

REFERENCES:
patent: 4491746 (1985-01-01), Koike
patent: 4559548 (1985-12-01), Iizuka et al.
patent: 4647956 (1987-03-01), Shrivastawa et al.
patent: 4670669 (1987-06-01), Cottrell et al.
patent: 4723081 (1988-02-01), Akatsuka
A. H. Taber, "Circuit Technique to Help Prevent CMOS Latch-Up", IBM, vol. 26, No. 10A, Mar. 1984.
"Prevent of CMOS Circuit Latch-Up", IBM, vol. 29, No. 5, 1986.
J. Lipman "Latchup Prevention in Bulk P-Well CMOS Circuit", VLSI Design, May/Jun. 1982.

Affiliated with

Also associated with

Rating

Latch-up prevention in a two-power-supply CMOS integrated circui does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Latch-up prevention in a two-power-supply CMOS integrated circui, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Latch-up prevention in a two-power-supply CMOS integrated circui will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-666300