Latch-up immune CMOS output driver

Details Latch-up immune CMOS output driver Latch-up immune CMOS output driver

1992-08-10

1995-02-14

Wolfe, Willis R.

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Signal transmission integrity or spurious noise override

327379, H03K 1710, H03K 190948

Patent

active

053898427

ABSTRACT:
An output driver for a CMOS circuit minimizes latch-up. A P-channel transistor (14) has its source-drain path coupled in series with the source-drain path of one or more N-channel transistors (16, 12). An internally generated high voltage VCCP, higher than VCC, is applied to the moat, well, or region in which the P-channel transistor is formed, and is applied to the gate electrode of the N-channel transistor(s). In one embodiment (FIG. 3), the source of the P-channel transistor is connected directly to VCC whereas in another embodiment (FIGS. 1A/1B), it is coupled to the source-drain path of another N-channel transistor, the gate electrode of which is coupled to the high voltage VCCP. In such second embodiment, the drain of the second N-channel transistor is coupled to VCC, so that the P-channel transistor is in series between the two N-channel transistors. One of the N channel FETs may receive at its gate electrode either a constant high voltage (VCCP) despite changes in the logic state of the data input signal (FIG. 1A), or it may correspond inversely therewith (FIG. 1B).

REFERENCES:
patent: 4039869 (1977-08-01), Goldman et al.
patent: 4475050 (1984-10-01), Noufer
patent: 4584491 (1986-04-01), Ulmer
patent: 4707625 (1987-11-01), Yanagisawa
patent: 4740713 (1988-04-01), Sakurai et al.
patent: 5057715 (1991-10-01), Larsen et al.
patent: 5220221 (1993-06-01), Casper

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