Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-09-02
2001-02-06
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C365S205000
Reexamination Certificate
active
06184722
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a latch-type sense amplifier and, in particular, to a latch-type high-speed sense amplifier having a low level differential small-swing input pair.
DESCRIPTION OF THE RELATED ART
Referring to
FIG. 1
, a first sense amplifier of the prior art receives an input pair signal which is high, i.e., around the supply voltage. This amplifier has output signals pre-charged to the high input signal level. Each input signal line is connected to a source/drain of a p-channel MOSFET (PMOS). A significant limitation is that it cannot amplify low level small differential signals, and is not therefore useful for applications requiring low level small differential amplification. Moreover, this prior art sense amplifier cannot have multiple shared inputs to the same latch.
Referring to
FIG. 2
, a second sense amplifier of the prior art receives an input pair signal which is low, i.e., around ground level and pre-charged to the input signal level. The problem with it is that it is undesirably slow, even compared with the sense amplifier of
FIG. 1. A
reason this second prior art sense amplifier is slow is that each output of its output pair is connected with a source/drain terminal of a PMOS transistor. This difference is significant because PMOS a PMOS transistor. This difference is significant because PMOS transistors have less drivability than n-channel MOSFETs (NMOS) do, and cause the amplifier to be slow. This second prior art sense amplifier further differs because respective source/drain terminals of the noted PMOS transistors are connected to source/drain terminals of NMOS transistors whose other drain/source terminals are each connected to an input of the input pair of the amplifier.
Another reason that the second prior art sense amplifier is slow is that it has an increased sensing delay due to two inverters. These inverters, which are added to obtain high pre-charged output signals, are each connected between an output and a source/drain terminal of one of the two NMOS transistors whose sources/drains are connected to inputs. Yet another problem with the second prior art sense amplifier is that it cannot receive multiple shared inputs to the same latch.
Referring to
FIG. 3
, a third sense amplifier of the prior art is disclosed in U.S. Pat. No. 5,534,800 to Hiraki et al. The Hiraki amplifier has a similar functionality as the first prior art amplifier shown in
FIG. 1
, wherein it functions to sense and amplify high level low differential input signals, and not low level signals. The Hiraki sense amplifier has a first pair of PMOS transistors, each with a source/drain terminal connected to an input. These PMOS transistors turn off during pre-charge, such that no data flows into the latch of the sense amplifier during pre-charge. The sense amplifier has a second pair of PMOS transistors which turn off when the sense amplifier is enabled. Further, the amplifier has two NMOS transistors, each connected to a drain/source terminal of one of the first pair of PMOS, which are pulled down after the sense amplifier is enabled and each of the second pair of PMOS turn off. Only after that is data received by each of the first pair of PMOS transistors of the latch. Thus, an undesirable time delay occurs during the operation of the Hiraki sense amplifier because the first pair of PMOS transistors turn off during pre-charge, and data enters through the second pair of PMOS transistors only after the NMOS transistors are pulled down.
Referring to
FIG. 4
, a fourth sense amplifier of the prior art is shown. This sense amplifier differs from the other prior art sense amplifiers noted above because each input is connected to a gate terminal of an NMOS transistor, rather than a source/drain terminal. This fourth prior art sense amplifier has applicability for amplifying high-level differential small-swing input pairs. It is not, however, satisfactory for use with low-level input pairs. This is because the low level inputs to the gates of each NMOS cause the NMOS to be off, rather than on, as would result from high level inputs to the gates of the NMOS.
SUMMARY OF THE INVENTION
The present invention solves the aforementioned problems in the prior art by providing a sense amplifier that can sense low level differential input quickly. The present invention provides a sense amplifier that can amplify low level differential small swing input signals.
Furthermore, the present invention provides a sense amplifier which is advantageously fast because each one of a pair of outputs is connected with a source/drain terminal of an NMOS transistor, wherein the NMOS has greater drivability than a typical PMOS.
In addition, the present invention can provide multiple shared inputs to the sense amplifier. A sense amplifier capable of having multiple inputs is a desired feature of plural embodiments of the present invention not shared by prior art amplifiers.
Another advantage of the present invention is realized wherein a first output switches from high level to low level and a second output remains at high level, when a low level differential small swing input signal pair reaches a threshold differential and thus a low level small swing input signal is sensed and amplified.
To achieve these desirable features and advantages, a latch-type sense amplifier of the present invention has a pair of input signal lines for receiving a pair of input signals forming a differential input signal pair. A pair of transistors of a first conductivity type each has a first and a third spaced apart terminals and a second terminal for controlling the flow of current between the first and third terminals. The first terminal of each transistor of the pair is connected to one of the input signal lines for receiving one of the input signals. The third terminal of each transistor of the pair is connected to the second terminal of the other transistor, forming one output of an output pair for supplying an output signal and its inverse. A pair of switching circuits controls the connection/disconnection between a voltage source and each of the third terminals of the transistor pair. The first output switches from high to low level and the second output remains at high level when the input signal pair reaches a threshold differential.
REFERENCES:
patent: 4523110 (1985-06-01), Johnson
patent: 4910713 (1990-03-01), Madden et al.
patent: 4973864 (1990-11-01), Nogami
patent: 5192878 (1993-03-01), Miyamoto et al.
patent: 5253137 (1993-10-01), Seevinck
patent: 5384733 (1995-01-01), Sueoka et al.
patent: 5386379 (1995-01-01), Ali-Yahia et al.
patent: 5408437 (1995-04-01), Cho et al.
patent: 5506524 (1996-04-01), Lin
patent: 5534800 (1996-07-01), Hiraki et al.
patent: 5563533 (1996-10-01), Cave et al.
patent: 5585747 (1996-12-01), Proebsting
patent: 5604705 (1997-02-01), Ackland et al.
patent: 5680356 (1997-10-01), Yamauchi
Cunningham Terry D.
Kabushiki Kaisha Toshiba
Limbach & Limbach L.L.P.
Tra Anh-Qua
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