Latch resistant insulated gate semiconductor device

Details Latch resistant insulated gate semiconductor device Latch resistant insulated gate semiconductor device

1995-03-03

1997-08-05

Jackson, Jerome

Active solid-state devices (e.g., transistors, solid-state diode

Regenerative type switching device

Emitter region feature

257165, 257166, 257580, 257582, 257401, 257341, 257342, H01L 29749

Patent

active

056545622

ABSTRACT:
An insulated gate semiconductor device (10) is fabricated by providing at least one ballast resistor (40) having a sheet resistance of at least one square. The ballast resistor (40) is formed in the emitter region (17) between two adjacent portions of the base region (26) at the top surface of the semiconductor body in which the device (10) is fabricated. The ballast resistor (40) improves the latch resistance of the device (10) in overload conditions.

REFERENCES:
patent: 4639754 (1987-01-01), Wheatley et al.
patent: 4860072 (1989-08-01), Zommer
patent: 5053847 (1991-10-01), Ito et al.
patent: 5321295 (1994-06-01), Hisamoto
patent: 5365082 (1994-11-01), Gill
patent: 5378911 (1995-01-01), Murakami
"Cell Geometry Effect on IGT Latch-Up," by Yilmaz, IEEE Electron Device Letters, vol. EDL-6, No. 8, Aug. 1985, pp. 419-421.
"MOS-Controlled Thyristors--A New Class of Power Devices," by Temple, IEEE Transactions on Electron Devices, vol. ED-33, No. 10, Oct. 1986, pp. 1609-1618.

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