Latch ratio circuit with plural channels

Details Latch ratio circuit with plural channels Latch ratio circuit with plural channels

2000-03-22

2001-09-04

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S208000, C327S214000, C327S218000

Reexamination Certificate

active

06285227

ABSTRACT:

FIELD OF THE INVENTION
This invention pertains to a ratio circuit, and in particular a MOS transistor ratio circuit for a latch and other digital circuits utilizing a ratio circuit.
BACKGROUND OF THE INVENTION
As illustrated by curve LA in
FIG. 14
, MOSFETS (metal-oxide semiconductor field-effect transistors) and other MOS devices exhibit the so-called short-channel effect, which is a phenomenon in which the threshold voltage V
th
decreases with the length of the channel or gate. When the short-channel effect is pronounced, punch-through takes place, so that the current between the source and drain cannot be controlled by the gate voltage. Consequently, in order to ensure normal functioning of MOS transistors, it is necessary to prevent the short-channel effect and punch-through.
Various technologies have been developed or proposed to suppress the short-channel effect. For example, a recent processing technology that uses a gate length of 0.21 &mgr;m as the design rule adopts the LDD (lightly doped drain) structure shown in FIG.
15
. In this structure, below the low-concentration diffusion region (N
−
) on the channel side end portion of the drain and source regions, the opposite conductivity type low-concentration diffusion region (P
−
) is formed by means of impurity ion implantation at a prescribed angle of incidence [&thgr;]. In this way, expansion from the drain and source regions to the depletion region can be effectively suppressed. Curve LB in
FIG. 14
shows a profile with maximum threshold voltage V
th
near the minimum gate length (0.21 &mgr;m) to satisfy the design rule. That is, the so-called inverse short-channel effect is realized.
The example shown in
FIG. 15
pertains to an N-channel MOS transistor. However, the same technology applies to the P-channel MOS transistor. In
FIG. 14
, characteristic curves LA and LB refer to the results of simulation and experiment for the N-channel MOS transistor, respectively. The same characteristic curves can be obtained with the P-channel MOS transistor. However, in this case, the rate of increase of V
th
in the inverse short-channel effect is a little smaller (lower).
FIG. 16
is a diagram illustrating an example of the conventional CMOS ratio circuit having the aforementioned MOS transistors with the inverse short-channel effect. In this ratio circuit, N-channel MOS transistor
202
of CMOS (complementary metal oxide semiconductor) circuit
200
forms the driving element, while P-channel MOS transistor
206
of CMOS circuit
204
on the other side forms the load element. The drain terminals of said N-channel MOS transistor
202
on the driving side and said P-channel MOS transistor
206
on the load side are electrically connected via transfer gate
208
. Usually, node
210
between said two transistors
202
and
206
is connected as the output terminal of this ratio circuit to the other circuit (not shown in the FIG.).
When both MOS transistors
202
on the driving side and MOS transistor
206
on the load side are on, transfer gate
208
is on. In this state, current i has the following circuit path: power source terminal of power source voltage Vdd→P-channel MOS transistor
206
on the load side→transfer gate
208
→N-channel MOS transistor
202
on the driving side→ground terminal.
In this ratio circuit, the conductance of MOS transistor
202
on the drive side is made higher than that of MOS transistor
206
on the load side. In this way, when both transistors are on, they are electrically mismatched, so that the output voltage at node
210
shifts toward the reference voltage (ground potential) on the side of MOS transistor
200
.
FIG. 17
illustrates the layout of two MOS transistors
202
and
206
. For MOS transistor
202
on the driving side, in order to raise the operating speed to the maximum, the gate length Li is set as the minimum gate length dimension (e.g., 0.21 &mgr;m) of the design rule, and, in order to increase the current capacity, the channel width Wi is selected to have a relatively large dimension (e.g., 0.91 &mgr;m). On the other hand, for MOS transistor
206
on the load side, in order to realize a load function with a high ON-resistance (a low conductance), the gate length Lj is selected to a dimension (e.g., 0.35 &mgr;m) significantly larger than the minimum gate length dimension. Also, channel width Wj is selected to have a dimension (e.g., 0.56 &mgr;m) smaller than that on the driving side.
In this way, since MOS transistor
202
on the driving side has gate length Li of the minimum gate length dimension of the design rule, operation is performed at a high threshold voltage Vth due to the inverse short-channel effect. On the other hand, for MOS transistor
206
on the load side, since the gate length Lj is significantly larger than the minimum gate length dimension of the design rule, operation is performed at a relatively low threshold voltage Vth without the influence of the inverse short-channel effect (also without the influence of the short-channel effect).
In recent years, with the progress made in realizing higher levels of integration and higher density of semiconductor ICs, in consideration of the reduction of power consumption, there has been a demand for the operation of various types of electronic equipment at lower power source voltage. In particular, there has been an increasing demand for guaranteeing the operation of portable battery-powered electronic equipment even when the power source voltage drops below 1 V.
The present inventors have extensively studied the performance and operation of the ratio circuit and found that in the conventional design method, due to influence of the inverse short-channel effect, there is an operating limit near 0.95 V. However, assuming a nominal voltage of 1.0 V, since there should be certain tolerance (margin), operation should be guaranteed down to 0.9 V, that is, 10% below the nominal voltage. Consequently, an operating limit near 0.95 V is insufficient.
Also, since the threshold voltage Vth of the MOS transistor rises as the temperature decreases, the influence of the inverse short-channel effect becomes stronger at low temperatures, and the operating limit value may become even higher.
FIGS. 18
,
19
and
20
respectively illustrate I
D
-V
GS
characteristic curves for three models of “WEAK,” “NOMINAL,” and “STRONG” obtained in the SPICE simulation in the case of the design of MOS transistors with channel width W selected as 0.21 (constant) and gate length L selected as 0.21 &mgr;m and 0.35 &mgr;m (two types) at ambient temperature of −40° C. For example, as can be seen from
FIG. 18
, threshold voltage Vth that corresponds to a given characteristic curve can be assumed to be the voltage value at the intersection of the straight line drawn tangent to the linear portion of the characteristic curve and the voltage axis.
Variations in the fabrication process lead to variations in device characteristics. In this example, the WEAK model refers to the fact that threshold voltage V
th
is relatively high and the current driving ability is relatively low (weak). On the other hand, the STRONG model refers to the case when threshold voltage Vth is relatively low and the current driving ability is relatively high (strong). The NOMINAL model refers to the intermediate case between the two aforementioned models. Also, for general-purpose conventional products, the Ta specification is 0 to 70° C. On the other hand, for communication ICs, it is in the range of −40° C. to 85° C. Consequently, −40° C. can be regarded as the worst-case temperature at which operation can be assured.
As can be seen from
FIGS. 18
,
19
and
20
, when the power source voltage (nearly equal to gate-source voltage V
GS
) of a MOS transistor with a gate length of 0.21 &mgr;m falls close to 0.9 V, the transistor will be operating in the sub-threshold region since the threshold voltage V
th
will have been raised by the inverse short-channel effect. In this sub-threshold region, since the S-factor is about 80 mV/d

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