Latch operating with a low swing clock signal

Details Latch operating with a low swing clock signal Latch operating with a low swing clock signal

2001-04-26

2003-02-25

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S210000, C327S211000

Reexamination Certificate

active

06525582

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a latch, i.e., a circuit which, for a first state of a clock signal, transmits without modification a datum present at its input and, for a second state of the clock signal, stores or locks the last state of the datum. The present invention more specifically relates to such a latch which operates with a low swing clock signal for the purpose of reducing the power consumed by the distribution of the clock signal.
2. Discussion of the Related Art
FIG. 1
show s a convention al latch. Datum D is applied on the input of an inverter
10
, the output of which is coupled to the input of an inverter
12
via a switch formed of the parallel association of an N-channel MOS transistor MN
1
with a P-channel MOS transistor MP
1
. Transistor MN
1
is controlled by a clock signal CK, while transistor MP
1
is controlled by the complement CK/ of this clock signal. The output of inverter
12
forms the output Q of the latch. This output Q is further connected to the input of an inverter
14
, the output of which forms a complementary output Q/ of the latch. This output Q/ is connected to the input of inverter
12
via a switch formed of the parallel association of an N-channel MOS transistor MN
2
with a P-channel MOS transistor MP
2
. Transistor MN
2
is controlled by complementary clock signal CK/ while transistor MN
2
is controlled by clock signal CK.
Two types of transistors are provided in each switch, since only one will be properly conductive according to the level of the signal to be transmitted. More specifically, the P-channel transistor will transmit the high levels of the signal, and the N-channel will transmit the low levels.
When clock signal CK is high, switch MN
1
-MP
1
is on whereas switch MN
2
-MP
2
is off. The state of datum D is then transmitted as is to output Q via inverters
10
and
12
.
When clock signal CK is low, switch MN
1
-MP
1
is off whereas switch MN
2
-MP
2
is on. Inverter
10
is disconnected from the input of inverter
12
whereas inverters
12
and
14
are connected head-to-tail to form a memory node which stores the state of signal D at the time when clock CK switched to the low state.
The power consumed to distribute the clock signal is proportional to CFV
2
, where C is the capacitance of the clock line, F is the frequency of the clock signal, and V is the peak-to-peak voltage, or swing, of the clock signal. Since integrated circuits become larger and larger and operate at higher and higher frequencies, the power consumed for the clock signal distribution becomes significant.
In recent circuits, it has been attempted to use a clock signal having a much lower swing than the nominal supply voltage of the circuit, which reduces considerably the consumed power, since the power increases with the square of the clock signal swing. For example, for circuits operating at a nominal voltage of 3.3 or 2.5 volts, one uses a clock signal varying between 0 and 1 volt, which reduces the consumed power by a factor 10 or 6, respectively.
However, some circuits, especially latches of the type of
FIG. 1
, cannot operate with a clock signal varying between 0 and 1 volt. Indeed, the 1-volt maximum value of clock signal CK or CK/ is too far from the nominal supply voltage to turn off P-channel MOS transistors MP
1
and MP
2
. Accordingly, when clock signal CK is low, and switch MN
1
-MP
1
is supposed to be off, transistor MP
1
is however capable of passing a high level which may cause a switching of the memory node formed by inverters
12
and
14
. Further, N-channel transistors MN
1
and MN
2
, controlled by a voltage close to their threshold voltage, are only slightly conductive and may even not be conductive at all if their sources are at a residual potential above the low supply potential. This may especially happen in the case of
FIG. 1
, where the sources of transistors MN
1
and MN
2
are connected to the low potential via transistors forming inverters
10
and
14
.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a latch which can operate with a low swing clock.
This and other objects are achieved by means of a latch including two first transistors of a first conductivity type connected to a first supply potential and controlled by a clock signal; two second transistors respectively connecting the two first transistors to an inverted output terminal and to a non-inverted output terminal and respectively controlled by a data line and a complementary data line; two third transistors of a second conductivity type respectively coupling the two second transistors to a second supply potential and cross-controlled by the output terminals; and means for maintaining the states of the output terminals when the first transistors are off.
According to an embodiment of the present invention, said means include two fourth transistors of the first conductivity type respectively connecting the output terminals to the first supply potential via a fifth transistor of the first conductivity type, and cross-controlled by the output terminals, the fifth transistor being controlled by an inverted clock signal.
According to an embodiment of the present invention, the on-state conductivity of the third transistors is lower than that of the series connection of one of the first transistors with one of the second transistors.
According to an embodiment of the present invention, the first conductivity type is type N, the first supply potential is a low potential, the second supply potential is a high potential, and the level of the clock signal varies between the low supply potential and a level lower than the high supply potential.
The foregoing objects, features and advantages of the present invention will be discussed in detail in the following non-limiting description of specific embodiments made in connection with the accompanying drawings.


REFERENCES:
patent: 4333020 (1982-06-01), Maeder
patent: 4356411 (1982-10-01), Suzuki et al.
patent: 4644185 (1987-02-01), Todd
patent: 5049760 (1991-09-01), Ooms
patent: 5748020 (1998-05-01), Mactaggart et al.
patent: 5821791 (1998-10-01), Gaibotti et al.
patent: 6278308 (2001-08-01), Partovi et al.
French Search Report from French Patent Application 97 12390, filed Sep. 30, 1997.

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