Latch circuit with metastability trap and method therefor

Details Latch circuit with metastability trap and method therefor Latch circuit with metastability trap and method therefor

2005-08-02

2005-08-02

Nguyen, Long (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S217000, C326S094000

Reexamination Certificate

active

06924682

ABSTRACT:
Methods and apparatus are provided for trapping metastability events to provide a metastable-free output signal. Values of an input signal compared to at least three different threshold voltages are latched at a predetermined point in time. A first intermediate signal is activate when all of the at least three corresponding latched values are in a first logic state. A second intermediate signal is activated when all of the at least three corresponding latched values are in second logic state. An output signal is placed in a first predetermined logic state in response to the second intermediate signal and is changed from the first predetermined logic state to a second predetermined logic state in response to the first intermediate signal.

REFERENCES:
patent: 5625309 (1997-04-01), Fucili et al.
patent: 6531905 (2003-03-01), Wang
patent: 6642763 (2003-11-01), Dike
patent: 6781429 (2004-08-01), Smith
Leroy Davis “Logic Design Information, Logic Metstability” (Online). 1998-2003 Retreived from the Internet: <URL: www.interfacebus.com/Design_MetaStable.html>.
Texas Instruments Inc. “Metastable Response in 5-V Logic Circuits”, Document No. SDYAA006, Feb. 1997.

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