Latch circuit tolerant of undefined control signals

Details Latch circuit tolerant of undefined control signals Latch circuit tolerant of undefined control signals

1986-10-21

1988-12-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 307585, 377 79, H03K 3013, H03K 3356, H03K 17687, H03K 19096

Patent

active

047942762

ABSTRACT:
A master slave latch circuit wherein the output impedances of the input and latching gates in both the master and slave sections are adjusted to prevent the two input gates from turning on simultaneously.

REFERENCES:
patent: 3720848 (1973-03-01), Schmidt
patent: 4250406 (1981-02-01), Alaspa
patent: 4399372 (1983-08-01), Tanimoto et al.
patent: 4484087 (1984-11-01), Mazin et al.
patent: 4554467 (1985-11-01), Vaughn
patent: 4613773 (1986-09-01), Koike
patent: 4703200 (1987-10-01), Zangara
patent: 4709173 (1987-11-01), Nishimichi et al.

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