Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1999-04-27
2003-06-17
Hjerpe, Richard (Department: 2775)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S099000, C345S100000, C345S559000, C377S064000
Reexamination Certificate
active
06580411
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a latch circuit for transmitting a pulse signal, a shift register circuit having this latch circuit and an image display device employing this shift register circuit.
Herein is provided a description for a conventional liquid crystal display device and a shift register circuit that constitutes the data signal line drive circuit and scanning signal line drive circuit of the device, which are taken as examples of an image display device and a shift register circuit having the conventional latch circuit. It is to be noted that the shift register and the image display device of the present invention are limited neither to the above liquid crystal display device nor to the shift register for the liquid crystal display device and is able to be applied to an image display device and a shift register for the image display device of another type.
Conventionally, as the above liquid crystal display device, there has been known a liquid crystal display device of an active matrix driving system. As shown in
FIG. 37
, this liquid crystal display device is constructed of a pixel array ARY, a scanning signal line drive circuit GD and a data signal line drive circuit SD. In the above pixel array ARY, pixels PIX are arranged in the vicinity of intersections of a number of scanning signal lines GL and a number of data signal lines SL that intersect each other and connected to the adjacent scanning signal line GL and data signal line SL so as to be arranged in a matrix form.
The data signal line drive circuit SD samples an input video signal dat in synchronization with a timing signal such as a clock signal cks and writes the resulting data into the data signal lines SL while amplifying the signal as the occasion demands. The scanning signal line drive circuit GD successively selects the scanning signal lines GL in synchronization with a timing signal such as a clock signal ckg, writes the video signal (data) dat written in the data signal lines SL into the corresponding pixels PIX by controlling the opening and closing of switching elements existing in the pixels PIX and holds the data written in the pixels PIX.
As shown in
FIG. 38
, each pixel PIX is constructed of a field-effect transistor SW that serves as the aforementioned switching element and a pixel capacity comprised of a liquid crystal capacity CL and an auxiliary capacity (added as the occasion demands) CS. Then, the data signal line SL and one electrode of the pixel capacity are connected to each other via the drain and source of the transistor SW, while the gate of the transistor SW is connected to the scanning signal line GL. Further, the other electrode of the pixel capacity is connected to a common electrode (not shown) common to all the pixels. In the above construction, the transmittance or reflectance of the liquid crystals is modulated by a voltage applied to the liquid crystal capacity CL, thereby driving the pixel for display.
A method for writing the aforementioned video signal dat into the data signal lines SL will be described next. As a system for driving the data signal lines SL, there are existing a dot sequence driving system and a line sequence driving system, and reference is herein made to the dot sequence driving system.
FIG. 39
shows a detailed circuit diagram of the data signal line drive circuit SD. The video signal dat inputted to a video signal line DAT is written into the data signal line SL by opening and closing a sampling circuit AS by means of an output pulse of each stage of a shift register circuit
1
synchronized with this video signal dat.
Describing the above more concretely, a signal of a sequence of output signals n of adjacent latch circuits SR constituting the shift register circuit
1
is amplified by a buffer circuit constructed of a plurality of inverter circuits, and an inversion signal is generated as the occasion demands to output a sampling signal s and its inverted signal /s to the sampling circuit (analog switch) AS. Then, the sampling circuit AS executes switching based on the sampling signals s and /s to supply the video data from the video signal line DAT to the data signal line SL. The clock signals cks and /cks to the latch circuits SR, output signals n
1
through n
3
of the latch circuits SR and sampling signals s
1
and s
2
in the above case are shown in
FIGS. 40A through 40G
.
FIG. 41
shows a detailed circuit construction of the scanning signal line drive circuit GD. In this scanning signal line drive circuit GD, the signal of the sequence of the output signals n of adjacent latch circuits SR that constitutes a shift register circuit
2
is obtained by NAND circuits, and by further taking an overlap with an external pulse width control signal gps, the desired pulse width is obtained. The clock signals ckg and /ckg to the latch circuits SR, the output signals n
1
through n
3
of the latch circuits SR, the pulse width control signal gps and scanning signals g
11
and g
12
to the scanning signal lines GL in the above case are shown in
FIGS. 42A through 42H
.
In this case, each latch circuit SR that constitutes the shift register circuits
1
and
2
in the data signal line drive circuit SD and the scanning signal line drive circuit GD has a construction as shown in FIG.
43
. It is to be noted that
FIG. 43
is an example of the latch circuit SR for constituting the shift register circuits
1
and
2
that can execute scanning only in one direction. In this case, a concrete construction example of a clocked inverter circuit
3
employed in the latch circuit SR is shown in FIG.
44
. By contrast, when constituting a shift register circuit that can execute bidirectional scanning, a latch circuit SR as shown in
FIG. 45
is employed. Either of these latch circuits SR is a half latch circuit, which latches the input signal with either one of the leading edge or the trailing edge of the clocks ck and /ck, outputs the output signal n of a pulse width of one cycle of the clocks ck and /ck.
In order to achieve the compacting, higher resolution, reduction in mounting cost and so on of liquid crystal display devices, a technique for integrally forming the pixel array ARY and the signal line drive circuits SD and GD, which manage the display, on an identical substrate is attracting a great deal of attention. In such a drive circuit integrated type liquid crystal display device, a transparent substrate must be employed as a substrate when constituting a transmission type liquid crystal display devices that are currently widely used. In the above case, it is often the case where a polysilicon thin-film transistor that can be formed on a quartz substrate or a glass substrate as an active element such as a transistor constituting the transistor SW of the pixel PIX or the clocked inverter circuit
3
.
However, the aforementioned conventional liquid crystal display device has the problems as follows. That is, as shown in
FIG. 39
, the data signal line drive circuit SD obtains the sampling signals s and /s on the basis of the signal of the sequence of the output signals n of adjacent two latch circuits SR. Therefore, as shown in
FIGS. 40A through 40G
, the trailing edge of the sampling signal s
1
corresponding to the adjacent data signal line SL
1
and the leading edge of the sampling signal s
2
corresponding to the adjacent data signal line SL
2
roughly coincide with each other.
Therefore, if the waveforms of the sampling signals s and /s become dull or a slight deviation occurs in terms of timing between output signals n from adjacent two latch circuits SR as a consequence of a characteristic change of the transistors that constitutes, for example, the data signal line drive circuit SD, then there is the possibility of the occurrence of overlap between the sampling signals s
1
and s
2
corresponding to the adjacent data signal lines SL
1
and SL
2
. In such a case, a noise is imposed on the data signal line SL, leading to a concern about the occurrence of troubles such as blur, ghost and crosstalk of the display imag
Kaise Yasuyoshi
Kubota Yasushi
Maeda Kazuhiro
Shiraki Ichiro
Washio Hajime
Conlin David G.
Edwards & Angell LLP
Hjerpe Richard
Jensen Steven M.
Lesperance Jean
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