Latch circuit operable as a D-type edge trigger

Details Latch circuit operable as a D-type edge trigger Latch circuit operable as a D-type edge trigger

1979-07-26

1981-07-07

Zazworsky, John

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307221R, 307291, H03K 3037

Patent

active

042776996

ABSTRACT:
A shift register latch circuit (FIG. 1) comprised of a polarity hold latch 1 connected to a set/reset latch 2. The latches can be clocked with separate non-overlapping clock trains (+A, +B and +C) so that automatically generated test patterns can be applied to a scan input S to test the circuit. This conforms to the so-called Level Sensitive Scan Design (LSSD) rules. During system operation, the shift register latch circuit operates as a `D` type edge trigger by connecting the clock input +B of the set/reset latch 2 to the clock -C supplied to the polarity hold latch 1. By connecting a number of shift register latches together a Johnson counter can be formed and by clocking all latches with a single oscillator, a series of non-overlapping clock trains can be produced. Implementations of the shift register latch in AND circuits or AND OR INVERT circuits are described.

REFERENCES:
patent: 3761695 (1973-09-01), Eichelberger
patent: 3783254 (1974-01-01), Eichelberger
patent: 3784907 (1974-01-01), Eichelberger
patent: 4006492 (1977-02-01), Eichelberger et al.
patent: 4051352 (1977-09-01), Eichelberger et al.
patent: 4051353 (1977-09-01), Lee
patent: 4063078 (1977-12-01), DasGupta et al.
patent: 4063080 (1977-12-01), Eichelberger et al.
T. W. Williams, "Single Clock Shift Register Latch" IBM Technical Disclosure Bulletin, vol. 16, No. 6, Nov. 1973, p. 1961.

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