Latch circuit including filter for metastable prevention

Details Latch circuit including filter for metastable prevention Latch circuit including filter for metastable prevention

1991-08-13

1993-02-16

Callahan, Timothy P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307234, 3072722, 328111, H03K 3284, H03K 3286, H03K 1716

Patent

active

051873850

ABSTRACT:
The latch circuit comprises a data hold circuit comprising a closed loop circuit formed by an even number of stages of logic gates connected in series. The data hold circuit accepts data when a clock signal is received and holds this data until a next clock signal is received. A filter is provided for eliminating pulses generated in the closed loop circuit. The filter is formed of logic gates.

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Diehl et al., "Considerations for Single Event Immune VLSI Logic" IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec. 1983.
Jenkins et al., "Metastability Resolution Latch" IBM Technical Disclosure Bulletin, vol. 23, No. 12, May 1981.

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