Latch circuit having two hold loops

Details Latch circuit having two hold loops Latch circuit having two hold loops

1987-03-11

1988-10-18

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307455, 3072721, H03K 3284, H03K 19086

Patent

active

047790113

ABSTRACT:
A latch circuit has two complementary hold loops therein for improving noise tolerance. The latch circuit includes a first gate for receiving a data and a first clock signal and outputting a first signal in response to a change in the clock signal. A second gate receives a second clock signal having an inverted polarity to that of the first clock signal. A third gate is operatively connected to output terminals of the first and second gates and outputs a first latch output. The latch circuit also includes a first hold line which supplies the first latch output to the second gate and a second hold line which supplies a second latch output of the latch circuit having an inverted polarity to that of the first latch output to the second gate. The second gate may have an inverted input terminal receiving the second latch output.

REFERENCES:
patent: 3178590 (1965-04-01), Heilweil et al.
patent: 3339089 (1967-08-01), Bergman
patent: 4045693 (1977-08-01), Ester
patent: 4439690 (1984-03-01), Maley et al.
patent: 4675553 (1987-06-01), Price et al.

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