Latch circuit having reduced input/output load memory and...

Details Latch circuit having reduced input/output load memory and... Latch circuit having reduced input/output load memory and...

2005-12-13

2005-12-13

Phan, Trong (Department: 2827)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S211000, C327S212000, C327S213000

Reexamination Certificate

active

06975151

ABSTRACT:
A latch circuit to perform high-speed input and output operations by reducing a load of an input circuit or an output circuit of the latch circuit. The latch circuit includes four or more inverters connected in a loop to hold a signal, a plurality of input terminals respectively connected to different nodes, and a plurality of output terminals respectively connected to different nodes. At least one input terminal of the latch circuit is used for normal operation of the latch circuit, and at least one input terminal is used for a test operation of the latch circuit. Further, at least one output terminal of the latch circuit is used for normal operation of the latch circuit, and at least one output terminal is used for a test operation of the latch circuit. The latch circuit reduces the number of circuit elements at a connecting point of an input terminal of the latch circuit or at a connecting point of an output terminal of the latch circuit. By reducing the number of circuit elements at the input or output connections, a load of the input or output can be reduced, and thereby high-speed input or output can be realized.

REFERENCES:
patent: 4390970 (1983-06-01), Kay
patent: 4835422 (1989-05-01), Dike et al.
patent: 5173626 (1992-12-01), Kudou et al.
patent: 5257223 (1993-10-01), Dervisoglu
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5550489 (1996-08-01), Raab

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