Latch circuit for a programmable logic device using dual n-type

Details Latch circuit for a programmable logic device using dual n-type Latch circuit for a programmable logic device using dual n-type

1988-12-30

1990-04-03

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307443, 307451, 307491, 307279, H03K 3356

Patent

active

049143182

ABSTRACT:
A latch circuit having a dual n-type driver transistors to provide an output which is compatible to TTL and CMOS. A complimentary pair of input signals is coupled to drive a pair of input transistors which are enabled by a clocking signal. The input transistors are driven by a cross-coupled inverters such that the output of each inverter is coupled to a gate of one or the other of the n-type driver transistors. The use of dual n-type transistors as a driver provides for a more symmetrical output wherein limiting the V.sub.oh of the output voltage provides for improved speed performance and reduces noise.

REFERENCES:
patent: 4810969 (1989-03-01), Fulkerson
patent: 4820942 (1989-04-01), Chan
patent: 4849653 (1989-07-01), Imai et al.

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