Latch circuit capable of reducing slew current

Details Latch circuit capable of reducing slew current Latch circuit capable of reducing slew current

1998-04-14

2000-12-19

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327208, 327210, H03K 3356

Patent

active

061631892

ABSTRACT:
A latch circuit for eliminating slew current flowing in between power sources during period when clock signal changes. In the latch circuit, an input terminal is formed in such a way that dual transfer gates are connected to respective nodes remaining differential signal of bistable circuit which is constituted that one pair of clocked.cndot.CMOS inverter is subjected to mesh connection. An output terminal of holding signal of latch circuit is drains of PMOS and NMOS transistors being adjacent to end terminal of power source, which transistors are member of the one pair of clocked.cndot.CMOS inverter. Gates of PMOS and NMOS transistors being adjacent to side of output terminal are taken to be input terminal of gate signal of the latch circuit. During period of sampling calculation, since there exists MOS transistor which is connected in series between power sources and which is sure to stand of OFF state, it is capable of cutting transient slew current flowing between power sources.

REFERENCES:
patent: 4506167 (1985-03-01), Little et al.
patent: 4569067 (1986-02-01), Ballup
patent: 5095225 (1992-03-01), Usui
patent: 5486777 (1996-01-01), Nguyen
patent: 5789956 (1998-08-01), Mahant-Shetti et al.
patent: 5808957 (1998-09-01), Lee et al.
Masakazu Shoji, "CMOS Digital Circuit Technology", Computing Science Research Center, AT&T Bell Laboratories, pp. 157-159, Prentice Hall, Englewood Cliffs, New Jersey, 07632, 1988.

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