Latch circuit capable of ensuring race-free staging for...

Details Latch circuit capable of ensuring race-free staging for... Latch circuit capable of ensuring race-free staging for...

2005-11-01

2005-11-01

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S208000, C327S217000, C327S218000, C326S094000, C326S095000

Reexamination Certificate

active

06960941

ABSTRACT:
A latch circuit capable of ensuring race-free staging for signals in dynamic logic circuits is disclosed. The latch circuit includes four separate logic gates. The first inputs of the first and second logic gates are connected to a first and second precharged internal nodes of the dynamic logic circuit, respectively. The second inputs of the first and second gates are connected to a first and second differential outputs of the dynamic logic circuit, respectively. The first inputs of the third and fourth gates are connected to an output of the first and second logic gates, respectively. The second input of the fourth gate is connected to an output of the third logic gate to provide a first output for the latch circuit. Similarly, the second input of the third logic gate is connected to the output of the fourth logic gate to provide a second output for the latch circuit.

REFERENCES:
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patent: 6271701 (2001-08-01), DiTommaso
patent: 6781411 (2004-08-01), Steiss et al.

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