Latch circuit and semiconductor integrated circuit having...

Details Latch circuit and semiconductor integrated circuit having... Latch circuit and semiconductor integrated circuit having...

1998-10-06

2002-06-11

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S225000, C327S544000, C365S229000

Reexamination Certificate

active

06404254

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit which can reconcile a high speed operation in an active mode and a low power consumption in a standby mode.
2. Description of Related Art
Recently, a demand for a low power consumption is increasing around the field of a portable electronic information instrument, and to meet with this demand, a low power supply voltage for the LSI has been advanced. Here, in a circuit constituted of MOSFETs, if the power supply voltage expressed with VDD and a threshold of the MOSFET is expressed with VT, an operation speed of the circuit constituted of MOSFETs is in proportion to about (VDD-VT)
2
. As a result, if the power supply voltage is greatly lowered, the operation speed abruptly drops. In other words, in order to reconcile a high speed operation in an active condition and a low power consumption in a standby condition, it is extremely difficult to greatly lower the power supply voltage.
On the other hand, in order to elevate the operation speed, if the threshold voltage VT is lowered, a subthreshold current which flows through the MOSFET in an OFF condition, increases, with the result that the power consumption in the standby condition in which the LSI does not operate, greatly increases. For example, if the threshold voltage is lowered by 0.1V, the subthreshold current flowing through the MOSFET of the OFF condition increases more than ten times.
In the field of the portable electronic information instrument, it is a matter of course that the high speed operation is required, but the power consumption in the standby condition is a large factor which determines the lift of the battery cell. Therefore, particularly in a region of the power supply voltage not greater than 2V, it is an important technical problem to be solved that the high speed operation and the low power consumption are compatible.
In order to make the high speed operation and the low power consumption compatible to each other, for example, Japanese Patent Application Pre-examination Publication No. JP-A-06-029834 (U.S. Pat. No. 5,484,774, the content of which is incorporated by reference in its entirety into this application) discloses a technology of setting the active mode and the standby mode and stopping the supplying of the electric power in the standby mode, thereby to realize the lower power consumption.
In the technology disclosed by the above referred publication, MOSFETs having two kinds of threshold are used, and therefore, this is called a “Multi-Threshold-CMOS technology” (abbreviated to “MTCMOS technology, and called a first prior art).
Now, the first prior art will be described with reference to FIG.
11
. In the shown example, logic circuits
11
a
and
11
b
are constituted of MOSFETs having a low threshold voltage, and have power terminals connected to quasi-power line QL
1
and QL
2
, respectively. The quasi-power line QL
1
and QL
2
are connected through power switches
101
and
102
to power supply lines PL
1
and PL
2
, respectively.
The power switches
101
and
102
are MOSFETs having a high threshold voltage, and supplied with control signals CS and CSB so as to be turned on in the active mode and off in the standby mode. If the size of the power switches
101
and
102
is set to be sufficiently large, the potentials of the quasi-power line QL
1
and QL
2
can be made substantially equal to those of the power supply lines PL
1
and PL
2
, respectively, in the active mode. As a result, the operation speed of the low threshold logic circuit is not almost deteriorated. In the standby mode, the power switches
101
and
102
are turned off, so that the supplying of the power is stopped, with the result that the low power consumption can be realized although the logic circuit is constituted of the low threshold MOSFETs.
Furthermore, the shown example includes an information hold circuit
11
c,
which is constituted of for example a latch circuit, which holds information in the standby mode. In this information hold circuit
11
c,
both of the high threshold MOSFETs and the low threshold MOSFETs are used. The low threshold MOSFETs are used in a circuit of determining the operation speed in the action condition, and power terminals of that circuit are connected to the quasi-power line QL
1
and QL
2
, respectively. The high threshold MOSFETs are used in a circuit of holding the information in the standby condition, and power terminals of that circuit are connected to the power supply lines PL
1
and PL
2
, respectively. With this arrangement, the power is supplied even in the standby mode, so that the information is held, and on the other hand, the low power consumption is realized.
In this MTCMOS technology, however, the design of the circuit for holding the information in the standby mode, is very important. Here, the latch circuit will be described as an example.
FIG. 12
is one example of the latch circuit used in the prior art (not the MTCMOS technology). The shown latch circuit includes complementary pass transistors
103
and
104
having respective gate terminals receiving a pair of complementary clocks CK and CKB. Furthermore, the latch circuit includes inverter circuits
105
and
106
, which are connected to power supply lines VCC and VSS, respectively. In this latch circuit, an input data is fetched by turning on the path transistors
103
and by turning off the path transistors
104
, and the information is held by turning off the path transistors
103
and by turning on the path transistors
104
.
FIG. 13
is one example of applying the latch circuit shown in
FIG. 12
to the MTCMOS technology. The shown latch circuit includes complementary path transistors
111
and
112
having respective gate terminals receiving a pair of complementary clocks CK and CKB. A pair of power supply terminals of an inverter circuit
113
are connected through power switches
116
and
117
to the power supply lines PL
1
and PL
2
, respectively. Gate terminals of these power switches
116
and
117
are supplied with the control signals CS and CSB, respectively, so that the power switches
116
and
117
are turned on in the active mode and are turned off in the standby mode. A pair of power supply terminals of inverter circuit
114
and
115
are connected to the power supply lines PL
1
and PL
2
, respectively.
The path transistors
111
and the inverter circuit
113
are constituted of the low threshold MOSFETs, and the inverter circuits
114
and
115
and the power switches
116
and
117
are constituted of the high threshold MOSFETs. Incidentally, the path transistors
112
can be constituted of either the low threshold MOSFETs or the high threshold MOSFETs, and the data fetching operation and the data holding operation are similar to those of the prior art latch circuit shown in FIG.
12
.
As mentioned above, since the path transistors
111
and the inverter circuit
113
are constituted of the low threshold MOSFETs, the high speed operation can be realized. In the standby mode, the path transistors
111
are turned off and the path transistors
112
are turned on so that the information is held in a loop composed of the path transistors
112
and the inverter circuits
114
and
115
. As mentioned above, since the inverter circuits
114
and
115
are constituted of the high threshold MOSFETs, the low power consumption can be realized.
However, this latch circuit has a problem in which the power switches cannot be used in common to other circuits. Even in the standby mode, an input potential and an output potential of the inverter circuit
113
are fixed by the inverter circuits
114
and
115
. Therefore, when the input potential is at a low level, an internal node
118
is connected to the power supply line PL
1
through a PMOS transistor of the inverter circuit
113
and a PMOS transistor of the inverter circuit
115
with a low impedance. When the input potential is at a high level, an internal node
119
is

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