Latch circuit and flip-flop circuit reduced in power consumption

Details Latch circuit and flip-flop circuit reduced in power consumption Latch circuit and flip-flop circuit reduced in power consumption

1998-08-07

1999-11-30

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, H03K 3037, H03K 3356

Patent

active

059949350

ABSTRACT:
A flip-flop circuit is constituted of two latch circuits of the same structure that are cascaded. The latch circuits each includes an inverter formed of a P channel transistor and an N channel transistor, an N channel transistor connected between a common node and a ground node, and two data input/output terminals. Two kinds of clock signals supplied to gates of N channel transistors are complementary to each other.

REFERENCES:
patent: 5391935 (1995-02-01), Gersbach et al.
patent: 5789956 (1998-08-01), Mahant-Shetti et al.
"3-Gb/s CMOS 1:4 MUX and DEMUX ICs", Yasuda et al., IEICE Transactions on Electronics, vol. E78-C, No. 12, Dec. 1995, pp. 1746-1753.

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