Latch circuit and clock signal dividing circuit

Details Latch circuit and clock signal dividing circuit Latch circuit and clock signal dividing circuit

2011-01-18

2011-01-18

Donovan, Lincoln (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S208000, C327S211000, C327S212000, C326S095000, C326S098000

Reexamination Certificate

active

07872514

ABSTRACT:
Latch circuit and clock signal dividing circuit comprises sequentially connected latch circuits. Each latch circuit has D-type latch with latch clock input, data input and data output. A difference detector is coupled to D-type latch, and has a difference output that provides a difference signal when data at input is different than data at output. Each latch circuit has an edge triggered gate that has gate clock input, output coupled to latch clock input and gate control input coupled to difference output of difference detector. In operation, when both a transition of clock signal supplied at gate clock input is detected by edge triggered gate, and the difference signal is provided to gate control input, will edge triggered gate allow an edge of a clock signal supplied at gate clock input to determine logic values supplied to latch clock input. As a result, data at input is transferred to output.

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