Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2000-08-11
2003-05-20
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S143000
Reexamination Certificate
active
06566928
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to a latch circuit constituted by a signal detecting circuit, a circuit for firmly holding this signal detection state until a power supply is interrupted, and a circuit for firmly releasing the signal detection state when the power supply is again turned ON.
2. Description of the Related Art
Conventionally, a latch circuit capable of holding a signal detection state is typically arranged as shown in a circuit arrangement of
FIG. 10
when an RS latch circuit is generally employed.
Referring now to the drawing, the conventional latch circuit will be explained.
First, a signal detecting circuit
2
detects an abnormal voltage of a specific terminal, an abnormal voltage of a power supply, and also an abnormal temperature. A detection output “S
SETX
” of this voltage detecting circuit
2
becomes an “L” level, namely active, and is connected to an SX terminal of an RS latch
1
. The RS latch
1
is constituted by a 2-input NAND gate and a 3-input NAND gate. When the voltage detecting circuit
2
detects an abnormal voltage and an abnormal temperature, an output S
CE
of the 3-input NAND gate which constitutes the output of this RS latch
1
becomes an “L” level. At this time, both a signal “S
RSTX1
” and another signal “S
RSTX2
” are set to an “H” level, which are entered into the reset input of the RS latch
1
. The output signal of the RS latch
1
constitutes an enable signal of another circuit, and also an enable signal of a system. For example, when the signal detecting circuit
2
detects that a short-circuit has occurred in a specific terminal, an abnormal heating phenomenon, or the like, the RS latch
1
causes operation of these failure circuits and systems to be stopped.
To again activate such a system which has stopped operating, the externally supplied reset signal S
RSTX2
is input to the RS latch
1
. Alternatively, since the power supply is again turned ON, the RS latch
1
is reset by receiving the signal S
RSTX1
corresponding to the output signal of the power-ON reset circuit
3
.
In general, there are some cases that a power-ON reset circuit may not firmly produce a reset signal, depending upon conditions occurring when a power supply is turned ON. As a result, even when such a power-ON reset circuit is not operable, a reset signal may be externally entered into a conventional latch circuit in order that an uncontrolled circuit may be reset.
For instance, in the case of a power-ON reset circuit shown in
FIG. 11
, when a power supply is turned ON, a potential of a node “A” is risen up to such a potential nearly equal to a power supply voltage because of a capacitive coupling phenomenon by a capacitor
5
. Thereafter, electron charges stored in the capacitor
5
are extracted therefrom by resistor
6
, so that the potential at the node A is decreased. Then, when this potential becomes lower than, or equal to an inverting voltage of an inverter
7
provided at a next stage, the output signal S
RSTX
of the power-ON reset circuit becomes an “H” level, and the reset signal is released.
In such a power-ON reset circuit, if the power supply voltage is risen at a slower speed than such a speed that the electron charges of the capacitor
5
are extracted by resistor
6
, then this power-ON reset circuit cannot produce the reset signal.
However, when the power-ON reset circuit is arranged by having the externally entered reset input, the terminal for receiving such an externally-supplied reset signal is additionally required, or the circuit capable of recognizing the reset command must be employed. Furthermore, there are certain possibilities that releasing operation of the latching action happens to occur, which is not originally required, due to noise contained in the signal. As a result, this may deteriorate reliability of the system.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above-described problem of the conventional reset circuit, and therefore, has an object to provide a reliable reset circuit.
To solve the problem as described above, according to a first aspect of the present invention, there is provided a latch circuit comprising means for detecting a signal, means for holding a signal detection condition and means for releasing the signal detection condition, characterized in that when a detection output produced from the detecting means is entered into the signal detection condition holding means, the signal detection condition holding means continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto, the signal detection condition releasing means produces a release signal only when the power supply is turned ON, and once the signal detection condition holding means holds the signal detection condition, the signal detection condition holding means is reset to an undetection condition only when the power supply is interrupted and then is again turned ON.
According to the present invention as set forth in the first aspect thereof, since the signal and the command are not externally input so as to reset the latch circuit, this latch circuit may not be unnecessarily reset due to noise, etc.
Further, in a latch circuit according to a second aspect of the present invention, the latch circuit is characterized in that while the signal detection condition holding means holds the detection condition, the latch circuit stops operation of a circuit into which the output signal of the signal detection condition holding means is inputted.
According to the present invention as set forth in the second aspect thereof, once the signal condition detecting means detects the abnormal condition to latch the latch circuit, the system and the circuit are firmly stopped until the power supply is again turned ON. As a consequence, it is possible to avoid such an unstable condition where the latch circuit is unwantedly reset and both the activation and deactivation of the circuit and system are repeatedly carried out.
Further, in a latch circuit according to a third aspect of the present invention, the latch circuit is characterized in that the signal detection condition releasing means is comprised of means for detecting a power supply voltage, means for determining producing time of a release signal and means for shaping a waveform, whereby the signal detection condition releasing means is equal to a power-ON reset circuit operated in such a manner that the release signal is continuously output after the power supply is turned ON until a preselected time period has passed, or the power supply voltage has reached a constant power supply voltage.
According to the present invention as set forth in the third aspect thereof, any of the pulse width of the reset signal and of the power supply voltage can be optimized. This reset signal is used to reset the RS latch employed in the latch circuit. For instance, even when the power supply voltage is gradually raised, the power-ON reset circuit can continuously output the reset signal until the power supply voltage is increased up to such a voltage at which the circuit can be sufficiently operated. Even when the power supply voltage is rapidly raised, since the sufficiently wide pulse width of the signal capable of resetting the latch circuit can be secured, the RS latch can be firmly reset by merely turning ON the power supply again, without employing such a means for inputting the externally-supplied reset signal.
Further, in a latch circuit according to a fourth aspect of the present invention, the latch circuit is characterized in that the power supply voltage detecting means included in the power-ON reset circuit is constituted by a depletion-mode N-channel MIS transistor and an enhancement-mode P-channel MIS transistor, both a gate and a source of the depletion-mode N-channel MIS transistor are connected to the ground potential, a drain of the depletion-mode N-channel MIS transistor is commonly connected to a drain of the enhancement-mode P-channe
Adams & Wilks
Lam Tuan T.
Seiko Instruments Inc.
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