Latch circuit

Details Latch circuit Latch circuit

1999-10-15

2001-05-29

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S199000

Reexamination Certificate

active

06239639

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a D-type latch circuit and a D-type flip-flop circuit that are composed of MOS field effect transistors.
2. Description of the Related Art
FIG. 6
illustrates a configuration of a conventional dynamic D-type flip-flop circuit
30
.
The dynamic D-type flip-flop circuit
30
includes a master latch
31
and a slave latch
32
. The master latch
31
includes a transfer gate
23
and an inverter
24
. The slave latch
32
includes a transfer gate
25
and an inverter
26
.
FIG. 7
illustrates a configuration of the transfer gates
23
and
25
shown in FIG.
6
. The transfer gate shown in
FIG. 7
includes a p-channel MOS field effect transistor
27
(hereinafter referred to as P-MOS transistor) and an n-channel MOS field effect transistor
28
(hereinafter referred to as N-MOS transistor). The source and drain of the P-MOS transistor
27
are connected to the source and drain of the N-MOS transistor
28
.
Referring to
FIG. 7
, when an input signal S is at a high level (hereinafter referred to as H level), an inverse input signal −S of the input signal S is at a low level (hereinafter referred to as L level). In this case, the P-MOS transistor
27
and the N-MOS transistor
28
are in the open state, and thus a signal A input to the transfer gate is output as a signal Y from the transfer gate.
When the input signal S is at the L level, the inverse input signal −S is at the high level. In this case, the P-MOS transistor
27
and the N-MOS transistor
28
are in the closed state, and thus the signal A input to the transfer gate is not output from the transfer gate.
FIG. 8
illustrates a configuration of an inverter. The inverter shown in
FIG. 8
includes a P-MOS transistor
29
and an N-MOS transistor
30
. The gate of the P-MOS transistor
29
is connected to the gate of the N-MOS transistor
30
. The source of the P-MOS transistor
29
is connected to a power source V
DD
. The source of the N-MOS transistor
30
is connected to a ground GND. The drain of the P-MOS transistor
29
is connected to the drain of the N-MOS transistor
30
.
The dynamic D-type flip-flop circuit
30
shown in
FIG. 6
receives clock signals BCK and −BCK.
FIG. 9
illustrates a clock generating circuit for generating the clock signals BCK and −BCK. The clock generating circuit shown in
FIG. 9
includes inverters
51
and
52
. The clock generating circuit shown in
FIG. 9
generates the clock signals BCK and −BCK from a clock signal CK.
FIG. 10
illustrates a configuration of a conventional static D-type flip-flop circuit
60
. The static D-type flip-flop circuit
60
includes a master latch
61
and a slave latch
62
. The master latch
61
includes transfer gates
35
and
38
, and inverters
36
and
37
. The slave latch
62
includes transfer gates
39
and
42
, and Inverters
40
and
41
. The transfer gates
35
,
38
,
39
, and
42
have the same configuration as that shown in FIG.
7
.
The conventional static D-type flip-flop circuit
60
is the same operation as that of the dynamic D-type flip-flop circuit
30
shown in FIG.
6
. However, for example, when the transfer gate
35
of the static D-type flip-flop circuit
60
is in the closed state, the transfer gate
38
is in the open state while holding a signal, which has been input to the transfer gate
35
in the immediately previous open state, in a circuit of the transfer gate
38
and the inverters
36
and
37
. Therefore, even when the transfer gate
35
is in the closed state, the signal which has been input to the transfer gate
35
in the immediately previous open state is output from the master latch
61
. The same applies to the slave latch
62
.
The conventional flip-flop circuits
30
and
60
require the clock signals BCK and −BCK having reversed polarities. In order to obtain the clock signals BCK and −BCK using the clock signal CK, the clock generating circuit shown in
FIG. 9
, i.e., the inverter, is necessary.
SUMMARY OF THE INVENTION
According to one aspect of this invention, a latch circuit includes a first circuit including an N-MOS transistor having a first electrode receiving a signal, a second electrode outputting the signal, a gate electrode, and a P-well, and a first inverter including input and output terminals. The second electrode of the N-MOS transistor is electrically connected to the input terminal of the first inverter, and the gate electrode of the N-MOS transistor is electrically connected to the P-well of the N-MOS transistor.
According to another aspect of this invention, a latch circuit includes a P-MOS transistor having a first electrode receiving a signal, a second electrode outputting the signal, a gate electrode, and an N-well, and a first inverter including input and output terminals. The second electrode of the P-MOS transistor is electrically connected to the input terminal of the first inverter, and the gate electrode of the P-MOS transistor is electrically connected to the N-well of the P-MOS transistor.
In one embodiment of the present invention, a latch circuit further includes a second circuit including a P-MOS transistor having a first electrode receiving a signal, a second electrode outputting the signal, a gate electrode, and an N-well, and a second inverter including input and output terminals. The second electrode of the P-MOS transistor is electrically connected to the input terminal of the second inverter, and the gate electrode of the P-MOS transistor is electrically connected to the N-well of the P-MOS transistor.
In one embodiment of the present invention, the first circuit serves as a master latch and the second circuit serves as a slave latch, a clock signal having a first or second level is input to the first and second circuits, the first circuit is in the open state when receiving the clock signal having the first level, the first circuit is in the closed state when receiving the clock signal having the second level, the second circuit is in the closed state when receiving the clock signal having the first level, and the second circuit is in the open state when receiving the clock signal having the second level.
In one embodiment of the present invention, the first circuit serves as a slave latch and the second circuit serves as a master latch, a clock signal having a first or second level is input to the first and second circuits, the first circuit is in the open state when receiving the clock signal having the first level, the first circuit is in the closed state when receiving the clock signal having the second level, the second circuit is in the closed state when receiving the clock signal having the first level, and the second circuit is in the open state when receiving the clock signal having the second level.
In one embodiment of the present invention, the first inverter includes an N-MOS transistor having a P-well and a gate electrode, and a P-MOS transistor having an N-well and a gate electrode.
In one embodiment of the present invention, the second inverter includes an N-MOS transistor having a P-well and a gate electrode, and a P-MOS transistor having an N-well and a gate electrode.
In one embodiment of the present invention, the absolute value of a threshold voltage of the N-MOS transistor included in the first circuit is smaller than the absolute value of a threshold voltage of the P-MOS transistor included in the first inverter.
In one embodiment of the present invention, the absolute value of a threshold voltage of the P-MOS transistor included in the second circuit is smaller than the absolute value of a threshold voltage of the N-MOS transistor included in the second inverter.
In one embodiment of the present invention, the first inverter includes an N-MOS transistor having a P-well and a gate electrode, and a P-MOS transistor having an N-well and a gate electrode, the second inverter includes an N-MOS transistor having a P-well and a gate electrode, and a P-MOS transistor having an N-well and a gate electrode, and the P-wells of the

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