Latch circuit

Details Latch circuit Latch circuit

1991-06-10

1992-04-07

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072722, 307454, 307455, 307480, 307355, 307356, H03K 19003

Patent

active

051031175

ABSTRACT:
Latch circuit including a differential amplifier T1, T2 for amplifying a data signal D, ND to be latched, applied to the inputs 1, 2 of the differential amplifier, a flip-flop T3, T7, T4, T8 for latching the amplified data signal across the load impedances 6, 7 which are connected to the transistors T1, T2 through switching transistors T5 and T6 if the clock signal CLK is high and are disconnected therefrom if the clock signal is low. When there is a high clock signal the emitter junctions 11, 14 of the flip-flop are currentless. The transistors T5 and T6 fix the voltage at these junctions, and thereby avoid a variation of the junction voltage. Consequently, the decision accuracy of the latching operation is retained even with high clock signal frequencies.

REFERENCES:
patent: 4542308 (1985-09-01), Winen et al.
patent: 4835771 (1989-05-01), Moussie

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