Latch cell family in CMOS technology gate array

Details Latch cell family in CMOS technology gate array Latch cell family in CMOS technology gate array

1987-07-20

1991-01-29

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307451, 307572, 307585, 307291, 377 61, H03K 326, H03K 19094, H03K 329

Patent

active

049888935

ABSTRACT:
The invention provides novel implementations of a latch cell in CMOS gate array technology to produce latch dissymmetry and permit a single ended data input. The dissymmetry is produced by increasing the output impedance of the second stage of the latch cell, which can be done, either in a DC or in an AC mode, or even in a mixed version of both modes.

REFERENCES:
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patent: 4558237 (1985-12-01), Rabe et al.
patent: 4728823 (1988-03-01), Kinoshita
patent: 4794283 (1988-12-01), Allen et al.
IEEE Transactions of Nuclear Science, vol. NS-30, No. 6, 12/83 "Considerations for Single-Event Immune VLSI Logic".
IBM TDB vol. 27, No. 7A, Dec. 1984 "Fast Shift Register Latch in CMOS Technology".
Patent Abstracts of Japan, vol. 9, No. 318 (E-366) [2041], Dec. 13, 1985; & JP-A-60 150 324 (Mitsubishi Denki K.K.) 08-08-1985.
Patent Abstracts of Japan, vol. 10, No. 297 (E-444) [2353], Oct. 9, 1986; & JP-A-61 113 319 (Mitsubishi Electic Corp.) 31-05-1986.
IEEE Transactions on Nuclear Science, vol. NS-30, No. 6, Dec. 1983, pp. 4501-4507, IEEE, New York, U.S.; S. E. Diehl et al.: "Considerations for Single Event Immune VLSI Logic" p. 4504, FIG. 3.

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