Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-08-30
2011-08-30
Rossoshek, Helen (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S104000, C716S106000, C716S108000, C716S111000, C716S113000, C716S117000, C716S128000, C716S132000, C716S136000, C703S014000, C703S019000, C703S025000
Reexamination Certificate
active
08010923
ABSTRACT:
A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.
REFERENCES:
patent: 5397749 (1995-03-01), Igarashi
patent: 6178539 (2001-01-01), Papadopoulou et al.
patent: 6543032 (2003-04-01), Zolotykh et al.
patent: 6556043 (2003-04-01), Garcia
patent: 7116131 (2006-10-01), Chirania et al.
patent: 7117143 (2006-10-01), Wang et al.
patent: 7219048 (2007-05-01), Xu
patent: 7346861 (2008-03-01), Lee
patent: 2006/0190224 (2006-08-01), Allen et al.
patent: 2009/0106719 (2009-04-01), Stevens
Yoshikawa et al.; “Timing optimization by replacing flip-flops to latches”; Publication Year: 2004; Design Automation Conference, 2004. Proceedings of the ASP-DAC 2004. Asia and South Pacific; pp. 186-191.
Wu et al.; “Storage optimization by replacing some flip-flops with latches”; Publication Year: 1996; Design Automation Conference, 1996, with EURO-VHDL '96 and Exhibition, Proceedings EURO-DAC '96, European pp. 296-301.
Lalgudi et al.; “Fixed-phase retiming for low power design”; Publication Year: 1996; Low Power Electronics and Design, 1996., International Symposium on; pp. 259-264.
Nakamura, Y.; “A design method for skew tolerant latch design”; Publication Year: 2008; Circuits and Systems, 2008. APCCAS 2008. IEEE Asia Pacific Conference on; pp. 356-359.
U.S. Appl. No. 11/361,370, filed Feb 24, 2006, Singh et al.
U.S. Appl. No. 11/361,369, filed Feb 24, 2006, Singh et al.
U.S. Appl. No. 11/805,954, filed May 25, 2007, Manaker, Jr. et al.
Burks, Timothy M. et al., “Critical Paths in Circuits with Level-Sensitive Latches,”IEEE Transactions on Very Large Scale Integration(VLSI)Systems, Jun. 1995, pp. 273-291, vol. 3, No. 2.
Hitchcock, R,. “Timing Verification and the Timing Analysis Program,”Proceedings of the 19thDesign Automation Conference, Jun. 14-16, 1982, pp. 446-456, Las Vegas, Nevada, USA.
Kourtev, Ivan S. et al., “Clock Skew Scheduling for Improved Reliability via Quadratic Programming,”Proceedings of the 1999 Int'l. Conference on Computer-Aided Design(ICCAD '99), Nov. 7-11, 1999, pp. 239-243, San Jose, California, USA.
Taskin, Baris et al., “Linearization of the Timing Analysis and Optimization of Level-Sensitive Digital Synchronous Circuits,”IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Jan. 2004, pp. 12-27, vol. 12, No. 1.
Taskin, Baris et al., “Time Borrowing and Clock Skew Scheduling Effects on Multi-Phase Level-Sensitive Circuits,”Proceedings of the 2004 International Symposium on Circuits and Systems(ISCAS '04), May 23-26, 2004, pp. II-617-II-620, vol. 2, Vancouver, British Columbia, Canada.
Chaudhary Kamal
Krishnamurthy Sridhar
Philofsky Brian D.
Rahut Anirban
Srinivasan Sankaranarayanan
Cartier Lois D.
Cuenot Kevin T.
Rossoshek Helen
Xilinx , Inc.
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