Latch based optimization during implementation of circuit...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S104000, C716S106000, C716S108000, C716S111000, C716S113000, C716S117000, C716S128000, C716S132000, C716S136000, C703S014000, C703S019000, C703S025000

Reexamination Certificate

active

08010923

ABSTRACT:
A computer-implemented method of implementing a circuit design within a programmable logic device can include selecting at least one circuit element of the circuit design. The selected circuit element can be converted to a latch. A timing analysis can be performed upon the circuit design after conversion of the selected circuit element to a latch. A determination can be made as to whether the timing of the circuit design improves and the conversion of the selected circuit element to a latch can be accepted when the timing of the circuit design improves. The circuit design can be output.

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