Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
2001-09-24
2002-07-02
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S202000
Reexamination Certificate
active
06414529
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a latch using a differential sense amplifier in a CMOS integrated circuit and a D-type flip-flop. More concretely, it relates to a latch mounting a differential sense amplifier using an inverter loop and a D-type flip-flop comprised using this as a master side latch and using an RS latch as a slave side latch.
2. Description of the Related Art
As one important element determining an operation frequency and/or power consumption of a CMOS VLSI, a D-type flip-flop can be mentioned.
Various procedures for raising the speed of a flip-flop and lowering the power consumption have continued to be proposed up to the present.
The D-type flip-flops announced in recent years include a D-type flip-flop referred to as a “sense amplifier-based flip-flop” (document: J. Montanaro et al., “A 160 MHz 32b 0.5 W COMS RISC Microprocessor”,
ISSCC Digest of Technical Papers
, pp. 214-215, February 1996).
Below, this D-type flip-flop will be referred to as a “differential sense amplifier type D-type flip-flop”.
This differential sense amplifier type D-type flip-flop is one type of master/slave flip-flop comprised of a combination of a master latch and a slave latch.
The conventional master/slave flip-flop is a combination of D-type latches.
Contrary to this, a differential sense amplifier type D-type flip-flop mounts a differential sense amplifier using an inverter loop for the master side latch, mounts an RS latch for the slave side latch, and combines them to realize a D-type flip-flop.
FIG. 16
is a circuit diagram of an example of the configuration of a conventional differential sense amplifier type D-type flip-flop.
This differential sense amplifier type D-type flip-flop
1
is comprised by a master side latch
2
and a slave side latch
3
connected in cascade via nodes H and H_X as shown in FIG.
16
.
The master side latch
2
has p-channel MOS (PMOS) transistors PT
21
to PT
24
, n-channel MOS (NMOS) transistors NT
21
to NT
26
, an inverter INV
21
, a synchronization signal input terminal T&PHgr;, a data input terminal TD, and data output terminals TQ and T_QX.
Sources of the PMOS transistors PT
21
to PT
24
are connected to a supply line of a power supply voltage V
DD
.
Drains of the PMOS transistors PT
21
and PT
22
are connected to the drain of the NMOS transistor NT
21
, and a connection node ND
21
thereof is connected to a gate of the PMOS transistor PT
23
, a gate of the NMOS transistor NT
22
, and the node H_X.
The drains of the PMOS transistors PT
23
and PT
24
are connected to the drain of the NMOS transistor NT
22
, and a connection node ND
22
thereof is connected to a gate of the PMOS transistor PT
22
, a gate of the NMOS transistor NT
21
, and the node H.
Then, gates of the PMOS transistors PT
21
and PT
24
are connected to the synchronization signal input terminal T&PHgr;.
The source of the NMOS transistor NT
21
is connected to the drain of the NMOS transistor NT
23
, and an intermediate node F_X is comprised by the connection point thereof. The source of the NMOS transistor NT
22
is connected to the drain of the NMOS transistor NT
24
, and an intermediate node F is comprised by the connection point thereof.
Sources of the NMOS transistor NT
23
and NMOS transistor NT
24
are connected to each other, and an intermediate node G is comprised by the connection point thereof. This intermediate node G is connected to the drain of the NMOS transistor NT
25
, and the source of the NMOS transistor NT
25
is connected to a ground potential GND.
Then, the source and the drain of the NMOS transistor NT
26
are connected to the nodes F and F_X.
A gate of the NMOS transistor NT
23
is connected to the data input terminal TD, a gate of the NMOS transistor NT
24
is connected to an output terminal of the inverter INV
21
, and an input terminal of the inverter INV
21
is connected to the data input terminal TD. A gate of the NMOS transistor NT
25
is connected to the synchronization signal input terminal T&PHgr;, and a gate of the NMOS transistor NT
26
is connected to the supply line of the power supply voltage V
DD
.
Also, the slave side latch
3
is comprised by 2-input NAND gates NA
31
and NA
32
.
A first input terminal of the NAND gate NA
31
is connected to the node H, and a second input terminal is connected to an output terminal of the NAND gate NA
32
and the output terminal TQ of the output data Q.
A first input terminal of the NAND gate NA
32
is connected to the node H_X, and a second input terminal is connected to an output terminal of the NAND gate NA
31
and the output terminal TQ_X of the inverted output data Q_X.
Next, a detailed explanation will be made of the operation of the conventional differential sense amplifier type D-type flip-flop
1
.
This flip-flop
1
fetches the value of the data input signal D in synchronization with a rising edge of the synchronization signal &PHgr; and outputs the same to the data output terminal TQ and the inverted data output terminal TQ_X. The value is held for one cycle of the synchronization signal &PHgr;.
In the period where &PHgr;=0, the PMOS transistors PT
21
and PT
24
become ON, and the NMOS transistor NT
25
becomes cut off.
FIG. 17
is a view of an equivalent circuit of the circuit of
FIG. 16
in this period where &PHgr;=0 and where the data input signal D=1.
In the period where &PHgr;=0, the PMOS transistors PT
21
and PT
24
equivalently behave as resistors, and the nodes H and H_X are precharged to the potential of complete logic 1 through them.
Then, the PMOS transistors PT
22
and PT
23
become cut off. The NMOS transistors NT
21
and NT
22
equivalently behave as diodes since the gate terminals and the drain terminals become the same potentials.
Accordingly, when the power supply voltage is V
DD
[V] and the threshold value of the NMOS transistor is Vtn, the potentials of the nodes F and F_X at this time an be estimated to be (V
DD
−Vtn) [V].
When &PHgr;=0, both of the output nodes H and H_X of the master side latch
2
have the logic 1. This operates NAND-RS latch of the slave side latch
3
as the hold mode.
When &PHgr; becomes equal to 1, the PMOS transistors PT
21
and PT
24
become cut off, the NMOS transistor NT
25
becomes ON, and the sense amplifier operates.
Either of the NMOS transistor NT
23
and the NMOS transistor NT
24
has become cut off according to state of the data input signal D and the inverted signal DX thereof. In the example of
FIG. 17
, the NMOS transistor NT
24
has become cut off.
At this time, a difference is produced in conductive resistances possessed by the nodes F and F_X with respect to the ground.
A view simply considering the conductive resistances of the nodes F and F_X is shown in FIG.
18
.
According to this
FIG. 18
, the conductive resistance possessed by the node F_X with respect to the ground becomes (r
23
+r
25
) &OHgr;, and the conductive resistance of the node F becomes (r
26
+r
23
+r
25
) &OHgr;.
Such a difference of conductive resistances appears in the discharge speed of charges on the nodes H and H_X. In this example, the conductive resistance possessed by the node F_X with respect to the ground is smaller, so the charge on the node H_X is more quickly discharged. At this time, also the charge on the node H is discharged.
However, due to the lowering of the potential of the node H_X, the PMOS transistor PT
23
becomes ON and the NMOS transistor NT
22
becomes cut off, and the potential of the node H which starts lower rises to obtain the potential of a complete logic 1 again.
In this way, a normal state is established in the inverter loop comprised by the PMOS transistors PT
22
and PT
23
and the NMOS transistors NT
21
and NT
22
.
Thereafter, even when the data input signal D and the inverted signal DX thereof change and the transistor which becomes cut off changes from the NMOS transistor NT
24
to the NMOS transistor NT
23
, this normal state is not destroyed.
This is because, either of the NMOS transis
Kananen, Esq. Ronald P.
Nuton My-Trang
Rader & Fishman & Grauer, PLLC
Sony Corporation
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