Single-crystal – oriented-crystal – and epitaxy growth processes; – Forming from vapor or gaseous state – With decomposition of a precursor
Reexamination Certificate
2002-08-06
2004-08-31
Hiteshew, Felisa (Department: 1765)
Single-crystal, oriented-crystal, and epitaxy growth processes;
Forming from vapor or gaseous state
With decomposition of a precursor
C117S041000, C117S084000, C117S104000, C438S151000
Reexamination Certificate
active
06783591
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the manufacturing of semiconductor devices, and more particularly, to an in-situ laser thermal anneal method for high dielectric constant (high-k) gate oxide films for complementary metal-oxide-semiconductor (CMOS) devices.
BACKGROUND OF THE INVENTION
Over the last few decades, the semiconductor industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices, and the most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One silicon-based semiconductor device is a complementary metal-oxide-semiconductor (CMOS) transistor. The CMOS transistor is one of the basic building blocks of most modern electronic circuits. Importantly, these electronic circuits realize improved performance and lower costs, as the performance of the CMOS transistor is increased and as manufacturing costs are reduced.
A typical CMOS semiconductor device includes a semiconductor substrate on which a gate electrode is disposed. The gate electrode, which acts as a conductor, is separated from the substrate by an insulating layer typically made from a gate oxide film, such as silicon oxide (SiO
2
). Source and drain regions arc typically formed in regions of the substrate adjacent the gate electrode by doping the regions with a dopant of a desired conductivity. The insulating layer is provided to prevent current from flowing between the gate electrode and the source, or drain regions.
In operation, a voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode, a transverse electric field is set up in the channel region below the gate oxide and between the source and drain regions. By varying the transverse electric field, it is possible to modulate the conductance of the channel region between the source and drain regions. In this manner an electric field is used to control the current flow through the channel region.
Since 1994, the International Technology Roadmap for Semiconductors (ITRS) has recommended a steady reduction in silicon device size, with an accompanying improvement in device performance, measured predominantly by circuit speed. The ITRS has served as a sort of “how-to” guide for the preservation of Moore's Law, the time-honored pronouncement of these ever-increasing component densities. While a variety of new materials and processes have been added to silicon process technology to maintain this rate of device scaling, the primary limitation has been in the area of photolithography and the ability to pattern and etch the ever-smaller device features. Recently, however, it has become clear that this steady scaling of feature sizes may be limited by the thickness of gate oxide films made of SiO
2
. This impending barrier has led to the development of new dielectrics as potential replacements for SiO
2
, known collectively as high-k dielectrics that do not limit the thickness of gate oxide films. Examples of possible high-k gate oxide materials include silicon oxynitride (Si
3
N
4
), oxynitrides (Si
x
N
y
O
z
), aluminum oxide (Al
2
O
3
), tantalum pentoxide (Ta
2
O
5
), hafnium oxide (HfO
2
), zirconium oxide (ZrO
2
), and barium strontium titanate (BaSrTiO
3
).
In any event, the formation of the high-k gate oxide film is such an early step in processing the CMOS device, that the high-k gate oxide film becomes critical to the quality of the finished CMOS device. In particular, it is important to obtain a high-k gate oxide film over the substrate that has a uniform thickness and a controlled microstructure. Accordingly, a need exists for an improved method of depositing a high-k gate oxide film over a substrate.
SUMMARY OF THE INVENTION
This and other needs are met by embodiments of the present invention which provide an improved method for forming a gate oxide film over a substrate including depositing at least one layer of a gate oxide film over a substrate using a chemical vapor deposition, and conditioning the layer of gate oxide film using laser thermal annealing in an in-situ manner.
The method of the present invention produces gate oxide films having a uniform thickness and a controlled microstructure. The method of the present invention also produces gate oxide films that are relatively free of stress, voids, and excess carbon and organic surface material.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 6455875 (2002-09-01), Takemura et al.
patent: 6620668 (2003-09-01), Lee et al.
Halliyal Arvind
Ramsbey Mark T.
Tripsas Nicholas H.
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