Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2002-09-30
2003-12-16
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S004000, C438S017000
Reexamination Certificate
active
06664142
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a type of laser repair. More particularly, the present invention relates to a laser repair operation of a silicon wafer before conducting a bump-forming process.
2. Description of Related Art
Integrated circuits are complicated electronic products whose manufacturing involves a series of major activities including integrated circuit design wafer fabrication, wafer testing and wafer packaging. In general, manufactured integrated circuits must undergo a series of tests before shipping just to ensure a high product quality. The results provided by these tests are essential also for repairing any malfunctional integrated circuits. As usual, natural yield of integrated circuit is relatively low. Hence, on discovering some defects in the circuit of a silicon chip, a laser repair operation is often conducted. In the repair process, a number of fuses are generally burnt by a laser so that specially designed redundant bit lines can replace the defective bit lines. Ultimately, product yield of the wafer may increase considerably.
FIGS. 1 through 4
are schematic cross-sectional views showing the progression of steps in a conventional laser repair operation. First, a silicon wafer is provided. The wafer has a plurality of silicon chips
100
. In
FIG. 1
, only a single silicon chip
100
is shown. The silicon chip
100
includes a plurality of bonding pads
102
, a plurality of testing pads
104
, a plurality of fuses
106
and a passivation layer
108
. The passivation layer
108
protects the silicon chip
100
and includes openings that expose the bonding pads
102
and the testing pads
104
.
As shown in
FIG. 2
, a probe
110
is used to carry out a testing operation. A probe mark
112
is formed on the testing pad
104
. When any defects are found in the circuit, a laser repair operation is next carried out. In a laser repair, a laser beam aims at a fuse
106
, burning a portion of the passivation layer
108
and melting open the protective fuse
106
to form a fused section
114
. Specially designed redundant bit lines then replace the defective bit lines. Through the laser repair operation, the yield of silicon chips on a wafer is greatly boosted.
As shown in
FIG. 3
, a bump-forming process is carried out after the laser repair operation. The bump-forming process in mainly includes under ball metallurgical (UBM) layer fabrication and bump production. Since the fabrication of the UBM layer often requires etching to form the pattern, a second passivation layer
116
is formed over the silicon chip
100
to prevent unwanted etchin of the testing pad
104
and the burnt section
114
. To be useful as a protective layer, the second passivation layer
116
needs also to undergo a photolithographic and etching process to form an opening
117
that exposes the bonding pads
102
.
As shown in
FIG. 4
, a conductive layer is formed over the chip
100
. Photolithographic and etching processes are conducted to form a bottom metallic layer
118
over the bonding pad
102
. Finally, a bump
120
is formed over the bottom metallic layer
118
, thereby completing the process of conducting a laser repair and fabricating bumps on a wafer.
Because a bump-forming process is carried out after a laser repair and an etching step is used to form the bottom metallic layer in the bump-forming process, a second passivation layer is required to protect the laser burnt fuse area. In addition, a masking step is required to form an opening that exposes the bonding pad in the second passivation layer so that a bump can be formed on the bonding pad. In general, the coating of a second passivation layer and the forming of an opening in the second passivation layer complicate the fabrication process and increase production cost.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a laser repair operation. The laser repair operation includes fabricating a bottom metallic layer on bonding pads and testing pads, conducting a testing operation by probing the bottom metallic layer on the testing pads, and finally performing a laser repair. Since etching that might damage the exposed fuse is no longer conducted after a laser repair, forming a second passivation for protecting the broken fuses is unnecessary.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of conducting a laser repair operation. A silicon wafer having a plurality of chips thereon is provided. Each chip has a plurality of bonding pads, a plurality of testing pads, a plurality of fuses and passivation layer for protecting the chip. The passivation layer exposes the bonding pads and the testing pads. A bump-forming process is conducted to form a bottom metallic layer and a bump sequentially over each bonding pad. A bottom metallic layer is formed over each testing pad. The bumps are formed, for example, by electroplating or printing. Thereafter, testing is carried out by probing various bottom metallic layers above the testing pads. Finally, a laser repair is conducted.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5326709 (1994-07-01), Moon et al.
patent: 5641701 (1997-06-01), Fukuhara et al.
patent: 6372522 (2002-04-01), Weling et al.
patent: 6395622 (2002-05-01), Liu et al.
Cuneo Kamand
Geyer Scott B
United Microelectronics Corp.
Wu Charles C. H.
Wu & Cheung, LLP
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