Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-06-25
2003-10-07
Jackson, Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S539000, C257S762000, C438S004000, C438S132000
Reexamination Certificate
active
06630723
ABSTRACT:
TECHNICAL FIELD
The invention relates to the laser adjustment or laser programming of laser fuses in integrated circuits. In particular, but not exclusively, the invention relates to the laser adjustment of integrated circuits in chips after packaging chip-size packages at wafer level (wafer level packaging).
BACKGROUND ART
In particular in the case of memory chips, adjustment of the circuit is required for setting a setpoint value. This adjustment is usually performed by electronic correction (for example electrical fuses) or laser-induced correction (for example laser fuses). In the case of electronic correction, implemented in the chip is a special electronic circuit, which allows electrical adjustment at the end of the production line. The disadvantage of this method is that the chip has to be increased in size by the surface area of the correction circuit (for example electronic fuse), which in turn increases the production costs. In the case of laser-induced correction, for example in the case of memory chips, laser light is used to disconnect laser fuses arranged within vias in the covering of polyimide. This takes place immediately after the completion of the wafers in the front end. Following the laser adjustment, the via openings must be closed again with a second polyimide layer, applied over a large area, to avoid short-circuits in the subsequent processes (metallization for the wiring) and to prevent corrosion of the laser fuses. Wiring is generally necessary in the case of chip-size packages (CSPs), since the spacing of the contact pads which lie near the laser vias on the front-end chip is too small to allow standard module boards to be used. This wiring, which is produced by electroplating, usually runs over the re-covered laser vias. After creating the wiring, the packaging and burn-in are performed. Since, however, the adjustment has already taken place, these later processes, possibly having adverse effects on the operation or functional ability of the circuit or the component, cannot be taken into account in the adjustment, since a laser intervention is no longer possible after the packaging. Consequently, components which exhibit additional defects precisely in these final working steps cannot be correctly adjusted, and possibly repaired. This results in increased wastage.
SUMMARY OF THE INVENTION
The object of the invention is to make it possible for integrated circuits to be programmed with laser light as late as possible in the production process, i.e. after the chip has been virtually or completely packaged, tested and a burn-in carried out, without the required surface area of the integrated circuit having to be increased.
This object is achieved by the method as claimed in claim 1 and the integrated circuit as claimed in claim 5. Preferred embodiments of the invention are the subject of the subclaims.
The invention is based on the realization that the laser adjustment carried out at the end of the production flow can lead to a simplification of the production process. This is possible in particular if packages of the CSP type are used. In the case of these packages, regions in which the laser intervention is to be performed are not buried too deep in the package, as is the case for example with a TSOP or BGA package.
The method according to the invention of programming an integrated circuit on a chip, with laser light, the integrated circuit having a plurality of laser fuses and being connected to a plurality of contact pads on the chip, and the chip being covered with a polymer layer which has at least windows on the plurality of contact pads, and comprising at least one wiring interconnect on the polymer layer which is electrically connected to at least one of the plurality of contact pads and ends at a predetermined location on a surface of the chip, is characterized in that the chip is irradiated in a predetermined region with intensive laser light, so that in the wiring interconnect there is created an interconnect opening, in the polymer layer lying thereunder there is created a layer opening and at least one of the plurality of laser fuses is interrupted in the predetermined region.
To be able to reduce the requirements for the power of the laser used as the radiation source, the wide interconnects preferably have a reduced interconnect thickness, at least in the predetermined region.
To produce the wide interconnects with a reduced interconnect thickness in at least one predetermined region, the creation of the at least one wide interconnect on the polymer layer comprises in particular the steps of: creating a seed layer on the polymer layer, creating a photoresist bridge on the seed layer over the laser fuses, creating a galvanic reinforcing layer on the seed layer and removing the photoresist bridge.
Preferably, the openings created by the laser light in the wiring interconnect and the polymer layer are covered by a printed polymer layer.
The integrated circuit produced according to the invention on a chip which has a plurality of laser fuses and is connected to a plurality of contact pads on the chip, the chip being covered with a polymer layer which has at least windows on the plurality of contact pads, and comprising at least one wiring interconnect on the polymer layer which is electrically connected to at least one of the plurality of contact pads and ends at a predetermined location on a surface of the chip, is characterized in that the at least one wiring interconnect has a reduced interconnect thickness over the at least one laser fuse.
In particular, the at least one wiring interconnect in the integrated circuit comprises a seed layer on the polymer layer and a galvanic reinforcing layer, which extends over the seed layer with the exception of over the laser fuse.
One advantage of the invention is that the production process is simplified as a whole: in the conventional technology, along with the contact pads laser vias must also be opened in the polymer covering layer by means of a highly accurate front-end photolithography. In the sequence according to the invention, this expensive step is no longer needed. Once laser programming has been performed, a second polyimide covering layer is applied, in order that the wiring can subsequently be created. In the new method, the opening of the contact pads is performed by a lower-cost back-end photolithography. The later covering of the laser openings can be performed by a simple polymer print.
Further features and advantages of the invention emerge from the following description of an exemplary embodiment, in which reference is made to the accompanying drawings.
REFERENCES:
patent: 6300233 (2001-10-01), Lee et al.
patent: 6420772 (2002-07-01), Kimmel et al.
Hedler Harry
Irsigler Roland
Infineon - Technologies AG
Jackson Jerome
Jenkins & Wilson & Taylor, P.A.
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