Laser-programmable interconnect process for integrated...

Details Laser-programmable interconnect process for integrated... Laser-programmable interconnect process for integrated...

1997-07-07

2001-07-10

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

Reexamination Certificate

active

06258633

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to laser-programmable electronic circuits. More particularly, this invention relates to laser-programmable electronic circuits fabricated using standard very large scale integration (VLS) process techniques.
2. Description of the Background Art
Microelectronic components constitute a major portion of the actual functioning elements of an electronic system. Integrated circuits (ICs) allow the unique functional elements of an electronic system to be realized. Thus, a large part of the cost and time associated with developing new electronic systems is the effort associated with developing new and unique ICs. Development costs can easily approach hundreds of thousands of dollars for each new IC designed and fabricated. Also, considering the fabrication of the ICs as well as design revisions after testing the newly-fabricated ICs, development times can be on the order of months. Hence, a significant problem facing the electronics industry is the cost and time associated with developing electronic systems and, in particular, ICs.
Programmable ICs have been developed to minimize the cost and time associated with developing customized ICs. Basically, programmable ICs are ICs that have been fabricated in generic yet programmable configurations. The programmability of a programmable IC thus allows customization in a rapid and cost-efficient manner. Specifically, cost effectiveness is achieved since the development cost of the programmable IC has been previously incurred and amortized across the volume of the programmable ICs produced and sold to various developers. The programming of the ICs typically may be done in a very short time relative to full custom-developed ICs.
Presently, there exist many different types of programmable ICs. A large class comprises programmable gate arrays (PGAs). PGAs have redundant logic gate elements distributed throughout the IC. Programming of a PGA occurs by connecting the logic elements into specific functional groups. The type of connection and the way that the connection is made varies among different vendors of PGAs. Many types of PGAs are user-programmable, and are generally referred to as field programmable gate arrays (FPGAs). FPGAs may be software-programmable whereas others are hard-programmable.
Software-programmable FPGAs use software-controllable switching elements, often referred to as programming elements, to direct the signal flow to various gates, thereby creating specific functional groups. One attribute of software-programmable FPGAs is that they can often be programmed after insertion into the developed electronic product. Also, reprogramming of the FPGA may occur without removing the FPGA from the electronic product. Unfortunately, however, software-programmable switching elements, such as pass transistors, consume considerable space on the IC, thereby limiting the number of gates that may be fabricated per a given IC die area.
In hardware-programmable FPGAs, the programming elements are typically “anti-fuse” elements composed of a highly-resistive material alloy that does not serve as a signal path. During programming, a high voltage is placed across the anti-fuse element to cause it to melt and form a conductive link at the interconnect, usually on the order of hundreds of ohms.
A more complete disclosure of FPGAs may be found in
Field
-
Programmable Gate Arrays
, authored by Stephen D. Brown, et al., and published by Kluwer Academic Publishers in 1992, the disclosure of which is hereby incorporated by reference herein. As set forth in
Field
-
Programmable Gate Arrays
, both hardware-programmable and software-programmable FPGAs are commercially available by a number of vendors, and have enjoyed significant commercial success. Unfortunately, however, as noted above, in software-programmable FPGAs, considerable chip area is required for the programmable elements and, in hardware-programmable FPGAs, the material alloys constituting the anti-fuse programmable element, requires specialized chip fabrication techniques.
More recently, PGAs have been developed that include programming elements that may be programmed by means of a laser. Representative laser-programmable PGAs are disclosed in the following United States Patents, the disclosures of each of which are hereby incorporated by reference herein:
4,240,094
Laser-Configured Logic Array
4,455,495
Programmable Semiconductor Integrated
Circuitry Including a Programming
Semiconductor Element
4,665,295
Laser Make-Link Programming of Semiconductor
Devices
4,872,140
Laser Programmable Memory Array
4,910,418
Semiconductor Fuse Programmable Array
Structure
4,937,475
Laser Programmable Integrated Circuit
5,049,969
Customizable Semiconductor Devices
More particularly, in U.S. Pat. No. 4,420,094, there is disclosed a laser-programmable logic array that employs laser technology to selectively tailor individual logic elements of which the building blocks of a large-scale integrated circuit (LSI) array may be configured and to selectively interconnect such laser-configured building blocks.
In U.S. Pat. No. 4,665,295, there is disclosed a laser-programmable semiconductor device that causes an electrical short between two conductors on a silicon substrate by melting the insulator between the conductors and fusing or shorting the conductors to a metal pad, thereby shorting or fusing the conductors together. Unfortunately, however, the necessity for the metal pad requires that specialized chip fabrication techniques be employed, thereby significantly increasing the cost of fabricating the semiconductor device.
In U.S. Pat. No. 4,872,140, there is disclosed a laser-programmable memory array that employs laser-fusible links. Similarly, in U.S. Pat. No. 4,937,475, there is disclosed a laser-programmable IC that employs laser-diffusible links composed of two back-to-back diodes that are separated by a gap of a few microns. Interconnection is accomplished by aiming a laser at the gap between the dopant regions of the diodes such that the dopant is caused to redistribute into the gap creating the interconnection. This technology has become known as “Lateral Diffused Link” (LDL) and has been employed at the wafer level in restructuring wafer scale integration (WSI) systems. Unfortunately, however, while LDL has been shown to be reproducible with high yield and good reliability, the resistance values of the interconnection are on the order of hundreds of ohms and some linkage to the substrate is sometimes experienced. Most importantly, LDL processes are limited to in-plane interconnects and, therefore, do not allow for vertical interconnections between adjacent layers of the IC. Further, it should be appreciated that the programmable ICs taught by both of these patents mandate specialized chip fabrication techniques in order to create the programmable links.
Therefore, it is an object of this invention to provide an improvement that overcomes the aforementioned inadequacies of the prior art devices and provides an improvement that is a significant contribution to the advancement of the laser-programmable IC art.
Another object of this invention is to provide an apparatus and method for producing an interconnect from a first metal trace, through a dielectric, to a second metal trace, comprising the steps of heating a portion of the first metal trace to cause thermal expansion thereof and at least partial melting of metal constituting the portion of the first metal trace and heating a portion of the second metal trace to cause thermal expansion thereof and at least partial melting of metal constituting the portion of the second metal trace such that the thermal expansion of the portions causes at least one crack in the dielectric to be formed between the portion of the first metal trace and the portion of the second metal trace and such that the melting of the metals of the portions of the first metal trace and the second metal trace causes the metals to fuse together through the crack, thereby producing the interconnect from the fi

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