Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – Fusible link or intentional destruct circuit
Reexamination Certificate
2000-11-02
2001-09-11
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
Fusible link or intentional destruct circuit
C365S225700
Reexamination Certificate
active
06288598
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to fuse circuits, and more specifically relates to a fuse circuit that uses a latch circuit or memory cell to store the data.
BACKGROUND OF THE INVENTION
Typically, fuse circuit structures are used in Application Specific Integrated Circuits (ASIC) for permanently storing a bit of information. There are more and more applications where it is desirable to use a fuse to store data (e.g. storing defective addresses in Built-In-Self-Repair, storing a unique identification number for some chips, etc.). A basic fuse is just a metal wire on the chip, where one end of the metal wire is connected to one of the logic levels and the other end of the metal wire is used to read the logic level. If the connected logic level is not desired, the end of the metal wire is blown using a laser machine. When the fuse is blown, the other end of the fuse will appear as floating logic. Hence, some circuitry must be used to provide opposite data for the open circuit.
A prior art fuse circuit structure design is illustrated in FIG.
1
. Specifically, the fuse circuit structure is shown within the dotted box
10
, and the remaining circuitry
20
is configured to read and hold the coded value in the fuse once it is coded. As shown, the design requires an extra flip flop to hold the data.
When the ENABLE signal is active:
If the fuse is blown, then the value at node D (the output
22
of the fuse) is “1” and when a clock edge is provided, the D value would go through multiplexer
24
and get stored in the first half-latch. The ENABLE signal can then be turned off.
If the fuse is not blown, then the value at node D (the output
22
of the fuse) is “0” and when a clock edge is provided, the D value would go through multiplexer
24
and get stored in the first half-latch. The ENABLE signal can then be turned off.
Once the coded value is read, the ENABLE signal is turned off. Even if the circuit is being clocked (CLK remains ON), then the stored value is fed back through the multiplexer xx and the read value is not effected.
A disadvantage to the circuitry illustrated in
FIG. 1
is that it requires the ENABLE signal to be kept ON for almost one half of the clock cycle, during which there is a direct path from VDD to VSS. This results in significant power consumption. Moreover, when the ENABLE signal is turned off, the circuitry requires a feedback path to store the coded and read data from the fuse. As shown in
FIG. 1
, the latch or flip-flop circuitry requires a number of transistors. If a simple and regular latch circuit is used at the output, the transistors used in the fuse circuit would need to be large in order to change the data inside the latch. Due to its static current, the latch circuit could burn the unblown fuse if it is enabled for a long enough period of time.
Another prior art fuse circuit structure design is illustrated in FIG.
2
. As shown, the structure uses a half latch circuit
30
that includes three transistors. When the fuse is not blown, the output will have logic 1, and when the fuse is blown, the output will have logic 0 (when power is up). As shown in
FIG. 2
, no flip-flop is needed to hold the data. The circuitry shown in
FIG. 2
also consumes significant power when the ENABLE signal is turned on because it would have a direct path from VDD to VSS.
Still other prior art suggests removing the transistor which connects to the ENABLE signal and relies on a capacitance divider to ensure that the circuit arrives in the correct state. However, since a half latch is used, it is possible that the incorrect output is generated if there is high ohm leakage resistance at the input of the inverter. The high ohm leakage resistance can “pull down” the inverter input to logic 0 before the feedback transistor turns on and supports pulling up the input of the inverter when the power is on.
OBJECTS AND SUMMARY
It is an object of an embodiment of the present invention to provide a fuse circuit which uses a latch circuit or memory cell to store data.
Another object of an embodiment of the present invention is to provide a fuse circuit which uses a full latch circuit instead of a half latch circuit and two pass gates in order to avoid leakage or stray resistance at an inverter input.
Still another object of an embodiment of the present invention is to provide a fuse circuit which has low power consumption, provides that there is no effect due to leakage/stray resistance, is capable of using the fuse data directly from the output of the fuse circuitry, and provides that a single port memory layout can be used for the actual transistors used in the fuse circuit.
Still yet another object of an embodiment of the present invention is to provide a fuse circuit which is very reliable, is small due to usage of single port memory and consumes very little power during power up setting.
Briefly, and in accordance with at least one of the foregoing objects, an embodiment of the present invention provides a fuse circuit that includes a fuse and a full latch connected to the fuse. The fuse circuit is configured to receive a plurality of input signals including a preset signal and an enable signal.
Preferably, a first pass gate is connected to the fuse and to the full latch and is configured to receive the enable signal and a second pass gate is connected to the full latch and is configured to receive the preset signal. Preferably, an output signal line is connected to the full latch and is configured to carry the output signal.
The fuse circuit is preferably configured to set the fuse using the preset signal. Ideally, the fuse circuit is configured to provide no direct path between VDD and VSS while using the preset signal to set the fuse. The fuse circuit is configured to provide an output signal which is dependent on the status of the fuse and the state of the enable signal. Specifically, the fuse circuit may be configured to provide that the output signal is of the same state as the enable signal if the fuse provides an open circuit and is configured to provide that the output signal is of a different state as the enable signal if the fuse provides a short circuit.
REFERENCES:
patent: 5566107 (1996-10-01), Gilliam
patent: 6118712 (2000-09-01), Park et al.
patent: 6215351 (2001-04-01), Le et al.
patent: 6236599 (2001-05-01), Goto
Agrawal Ghasi
Huang Johnnie
LSI Logic Corporation
Tran Toan
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