Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2001-05-24
2003-08-19
Pert, Evan (Department: 2829)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
Reexamination Certificate
active
06607945
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
This invention relates generally to semiconductor fabrication technology and, more particularly, to techniques for programming semiconductor devices.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate dielectric thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the FET, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors. Additionally, reducing the size, or scale, of the components of a typical transistor also increases the density, and number, of the transistors that can be produced on a given amount of wafer real estate, lowering the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
However, reducing the channel length of a transistor also requires reducing the size and area of electrical contacts to active areas, such as N
+ (P
+
) source/drain regions and a doped-polycrystalline silicon (doped-polysilicon or doped-poly) gate conductor. As the size and area of the electrical contacts to the active areas get smaller, the active area contact resistance increases. Increased active area contact resistance is undesirable for a number of reasons. For example, increased active area contact resistance may reduce device drive current, and source/drain current through the device, and may also adversely affect the overall speed and operation of the transistor.
Typically, depositing titanium (Ti) or cobalt (Co) on the active area electrical contacts may decrease active area contact resistance. The Ti may then be silicided by annealing with a heat-treatment to form titanium silicide (TiSi
2
) at the active area electrical contacts (self-aligned silicidation or salicidation). The salicided TiSi
2
lowers active area contact resistance.
Silicide fuses may also be formed between semiconductor devices. Typically, when the circuit design and/or layout for the various semiconductor devices has been decided, appropriate ones of the silicide fuses between the respective semiconductor devices may be “blown” to separate electrically the appropriate semiconductor devices from one another. During programming of conventional silicide fuses, a relatively high voltage of about 2 V or higher drives a current through the silicide fuses to increase the local temperature in the silicide fuses through Joule heating to induce an irreversible phase transition of the silicide. The temperature required for the irreversible phase transition of the silicide is about 900° C. Under optimized conditions, the new phase produces agglomeration of the silicide and increases the resistance through the silicide fuse by as much as about 20 times the “unblown” resistance.
However, reducing the size, or scale, of the components of typical semiconductor devices, such as field effect transistors, also typically requires reducing the operational voltage of such semiconductor devices. The programming procedure for the silicide fuses between such semiconductor devices, however, becomes much more difficult as the semiconductor device operational voltages, and, consequently, the maximum allowable silicide fuse “blowing” voltages, are reduced to less than about 2 V. Voltages this low typically lead to an incomplete phase transition for the silicide fuses and the resistances may only increase partially, to a range of only about 3-5 times the “unblown” resistances. This resistance increase may not be sufficient for the programming of the silicide fuses and normal device operation.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
In one aspect of the present invention, a method is provided, the method comprising programming a silicide fuse by passing a current through the silicide fuse while substantially simultaneously irradiating the silicide fuse with a laser.
REFERENCES:
patent: 4535219 (1985-08-01), Sliwa, Jr.
patent: 5389814 (1995-02-01), Srikrishnan et al.
Advanced Micro Devices , Inc.
Pert Evan
Williams Morgan & Amerson
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