Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
1999-10-18
2003-09-23
Clark, Jasmine J B (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S713000, C257S752000, C257S773000
Reexamination Certificate
active
06624524
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to the field of integrated circuit fabrication. More specifically, the present invention is structure and a technique for fabricating a structure useful for aligning a wafer, substrate, or integrated circuit die.
There are many circumstances where aligning a wafer or integrated circuit die is important. For example, alignment is important during the processing of integrated circuits. Integrated circuits are fabricated using a layer-by-layer process. Alignment may be critical during the processing of certain layers, where these layers must to aligned properly in relationship to previous layers. For example, a contact layer must be aligned properly with a first conductor layer in order to create contacts at the correct locations. Contacts formed at the wrong locations may create shorts or opens, and reduce yield.
Proper alignment is also critical in many other situations. These include testing of,an integrated circuit die on a wafer. The die must be positioned properly in order to properly probe the device.
Moreover, alignment is also important when programming or configuring an integrated circuit. For example, a die may have fuses that are to be laser programmed. The fuses may be made of polysilicon, or another conductor. This fuse may couple together two (or more) devices or conductors. A laser with sufficient energy is directed at the fuse. The laser “blows” the fuse, decoupling the two devices or conductors. In order for the laser to properly reference the coordinates of a fuse, the integrated circuit must be aligned properly. When the integrated circuit is not aligned properly, the laser may damage or destroy a portion of the circuitry instead of blowing the desired fuse. Therefore, the alignment of an integrated circuit or wafer is especially critical.
A wafer or integrated circuit die may need to be aligned properly in an X-direction, Y-direction, rotation angle, and other orientation. As technology improves, alignment is becoming more important and critical, especially resulting from the continued scaling and shrinking of semiconductor device geometries. Integrated circuits (or “chips”) have progressively become smaller and denser, and any small misalignment will adversely affect the integrated circuit yield and functionality of the integrated circuit.
One technique of alignment is by use of an alignment target. An alignment target should have good reflective or optical contrast so it can be easily identifiable. For example, a laser may be used to determine a change in reflectivity or optical contrast in a semiconductor structure used as the alignment target. This contrast may be achieved by forming a region with rough topography and a region with a smooth topography, where these regions are in close proximity to one another. Light is reflected from the smooth or planar region while light is scattered from the rough region. A laser alignment system would find this alignment target and align the wafer or integrated circuit based on the target.
In order to facilitate the fabrication of smaller device sizes, current process technologies emphasize relatively smooth or planar topographies. Smooth topographies allow better step coverage and allow packing of devices and geometries closer together. Some of the techniques used to form flat topographies include such processing techniques as chemical-mechanical polishing (CMP). With CMP, process layers (e.g., dielectrics) are mechanically polished with a slurry mixture to form a very flat topography. A further technique includes plug technology (e.g., tungsten plug technology), where a plug material is used to fill contacts or vias, or both, in order to minimize step coverage (i.e., metal step cover over plugs may be near 100 percent). Plug technology further emphasizes a flat or planar topography.
Despite the substantial success of such planarized process technologies, these processes also meet with certain limitations, especially when used to create a region having good reflectivity, which may be used as an alignment target. With flat or smooth topographies, the resulting structures and regions will have a similar optical reflectiveness. This leads to poor reflective or optical contrast, making it difficult (and possibly impossible) to align a wafer or integrated circuit die, especially by using laser. Furthermore, in some processes, metals use antireflective coatings, further reducing the reflectivity contrast over flat topography.
As can be seen, a structure and technique for fabricating a good reflective contrast is needed, especially where this structure is useful as an alignment target for aligning a wafer or integrated circuit.
SUMMARY OF THE INVENTION
The present invention is a structure and technique for fabricating a structure having good reflective contrast for use as an alignment structure. In particular, a technique of the present invention is for fabricating a structure having a rough topography using a planarized semiconductor process. The rough topography structure of present invention has a different reflectivity compared to a smooth or planar topography structure. Specifically, the rough topography will scatter incident radiation and light, while the smooth topography will reflect radiation and light. A structure including both rough and smooth topographies may be used as an alignment target for aligning an integrated circuit or wafer. The system will be able to identify the reflective and optical contrast between the smooth and rough topography. After alignment, an integrated circuit, such as a memory, microprocessor, or programmable logic device, may be programmed, such as by a laser to blow laser-programmable fuses.
The technique of the present invention includes forming an initial cored region in a plug filling a contact opening. This cored region is nonplanar and has a depression in about the middle of the contact opening. Subsequent process layers are formed on top of this depression. The subsequent process layers also have a depression and are nonplanar above the cored region in the contact layer. The subsequent process layers generally aggravate or augment the nonplanar characteristics of the cored region. Also, subsequent via layers may also be cored, similar to the contact layer, to further enhance the roughness of the topography.
More specifically, the method of forming a rough topography on a substrate using a planarized process of the present invention includes the following steps. A contact opening is formed where a lateral dimension of the contact opening exceeds a minimum contact size. The contact opening is filled with a first plug layer. The first plug layer is etched back to create a first cored region in the first plug layer. The first cored region has a first depression. A subsequent process layer is formed and stacked on the first cored region. The subsequent process layer has a second depression formed on top of the first depression. In a specific embodiment, at least one lateral dimension of the contact opening exceeds about 1.5 times the minimum contact size.
Moreover, an alignment structure for semiconductor fabrication of the present invention includes a smooth and a rough region formed on a substrate. The rough region includes a first conductive layer and a second conductive layer formed above the first conductive layer. A first insulating layer is formed between the first and second conductive layers. The first insulating layer has a first opening for electrically coupling the first and second conductive layers. A plug layer, having a cored region, fills the first opening. The topographical roughness formed by the cored region scatters incident radiation.
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patent: 49
Altera Corporation
Clark Jasmine J B
Townsend and Townsend / and Crew LLP
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