Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Patent
1998-03-13
1999-12-14
Saadat, Mahshid
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
774773, 774752, H01L 2348, H01L 2352, H01L 2940
Patent
active
060021829
ABSTRACT:
A technique to form a structure with a rough topography (415) in a planarized semiconductor process. The rough topography (415) is formed by creating cored contacts (433). Subsequent process layers may be further stacked on top of the cored contacts in order to augment the nonplanar characteristics of the cored contacts. This rough topography structure may be used to align integrated circuits and wafers. An integrated circuit may be laser aligned using this alignment structure.
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Altera Corporation
Clark Jhihan B.
Saadat Mahshid
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