Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system
Reexamination Certificate
1998-10-29
2001-07-24
Teska, Kevin J. (Department: 2763)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
C703S002000, C703S014000, C716S030000
Reexamination Certificate
active
06266629
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to Pseudomorphic Heterojunction Electron Mobility Transistors (PHEMTs) and more particularly to methods for modeling such transistors.
As is known in the art, PHEMTs are used in power amplifiers and low noise amplifiers in a wide range of military and commercial applications. Because of its high efficiency operation, high gain (even near pinch-off) and low noise figure, the PHEMT has replaced the MESFET in radar and communication applications for frequencies ranging from S-Band through mm-wave. The excellent performance of the device, however, is not backed by adequate large signal models essential in MMIC power amplifier design to accurately predict output power, power added efficiency (PAE), harmonic power, third order intermodulation distortion, and adjacent channel power ratio.
Traditionally, the model formulations developed for the MESFET have been adapted to the PHEMT with mixed results, based on the frequency of operation. The error in this approach has been that one of the most critical model parameters; namely, the gate charge has been modeled with simplistic formulations. As a result, the input capacitance nonlinearities have been inadequately modeled, resulting in inaccurate large signal prediction of fundamental quantities such as power and efficiency with even larger discrepancies in harmonic power and 3rd order intermodulation distortion. Recent papers such as: “Analytical Charge Conservative Large Signal Model for MODFETs Validated up to mm-Wave Range” by R. Osorio, M. Berroth, W. Marsetz, L. Verweyen, M. Demmler, H. Massler, M. Neumann, and M. Schlechtweg, published in the IEEE MTT-S Digest, pp.595, 1998; and “Improved Prediction of the Intermodulation Distortion Characteristics of MESFETs and PHEMTs Via a Robust Nonlinear Device Model”, by V. I.Cojocaru and T. J. Brazil, published in IEEE MTT-S Digest, pp.749, 1998, have used more complex expressions for the gate charge with excellent results, but the model verification has been limited to small periphery devices, generally less than 400 &mgr;m.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method is provided for large signal modeling of a field effect transistor. The method includes establishing a small signal model for the transistor, such model having a gate-source capacitance C
gs
and a drain-gate capacitance C
dg
, both being functions of a gate-source voltage V
gs
and a drain-source voltage V
ds
. The s-parameters of the transistor are measured and curve fitting is applied to the measured s-parameters to establish small signal model parameters. The small signal model parameters include gate-source capacitance C
gs
as a function of V
gs
and V
ds
and gate-drain capacitance C
dg
as a function of V
gs
and V
ds
. Curve fitting is applied to C
gs
and C
dg
to establish large signal gate charge fitting parameters. The established large signal gate charge fitting parameters are used to express a gate-source charge Q
gs
and a gate-drain charge Q
gd
as functions of V
gs
and a gate-drain voltage V
gd
in a large signal model for the transistor.
A two terminal voltage dependent gate charge expression Q
g
=f (V
gs
,V
gd
)=Q
gs
+Q
gd
has been obtained that describes PHEMT gate capacitances C
gs
and C
dg
, where C
gs
represents capacitance between the gate and the source of the transistor; C
dg
represents capacitance between the gate and drain of the transistor; V
gs
represents voltage between the gate and the source of the transistor; and, V
gd
represents voltage between the gate and the drain of the transistor. More particularly the equation for Q
g
is expressed as:
Q
g
=
[
(
C
110
-
C
11
th
)
2
f
(
V
j1
)
+
C
11
th
(
V
j1
-
V
cgs
)
]
[
1
+
λ
(
V
0
-
V
ds0
)
]
-
C
12
sat
V
j2
where: C
110
, C
11th
, V
cgs
, &lgr;, V
ds0
and C
12sat
are gate charge fitting parameters;
f
(
V
j1
)=
V
j1
−V
cgs
+(1
/A
cgs
)1
n
(cos
h
(
A
cgs
*(
V
j1
−V
cgs
)));
V
j1
=&ggr;
2
*((1+&agr;)*
V
gs
−V
ds
+&bgr;(
V
ds
2
+&dgr;
ds
2
)
0.5
);
V
j2
=&ggr;
2
*((1+&agr;)*
V
gs
−V
ds
−&bgr;(
V
ds
2
+&dgr;
ds
2
)
0.5
);
V
0
=(
V
ds
2
+&dgr;
ds
2
)
0.5
;
and A
cgs
, &ggr;
2
, &agr;, &bgr;, and &dgr;
ds
are gate charge fitting parameters.
The gate capacitances C
gs
and C
dg
are functions of two terminal voltages V
gs
and V
gd
, and are obtained by taking the derivatives of Q
g
, as follows:
C
gs
=&dgr;Q
g
/&dgr;V
gs
C
dg
=&dgr;Q
g
/&dgr;V
gd
C
gs
=&dgr;Q
g
/&dgr;V
gs
=C
1
*(1+&lgr;*(
V
0
−V
ds0
))*&ggr;
2
*(&agr;+&bgr;*
V
ds
/V
0
)+
C
2
*&lgr;*V
ds
/V
0
−&ggr;
2
*C
12sat
*(&agr;−&bgr;*
V
ds
/V
0
);
C
dg
=&dgr;Q
g
/&dgr;V
gd
=C
1
*(1+&lgr;*(
V
0
−V
ds0
))*&ggr;
2
*(1
−&bgr;* V
ds
/V
0
−C
2
*&lgr;*V
ds
/V
0
&ggr;
2
*C
12sat
*(1
+&bgr;*V
ds
/V
0
);
where:
C
1
=((
C
110
−C
11th
)/2)*(1+tan
h
(
A
cgs
*(
V
j1
−V
cgs
)))+
C
11th
C
2
=((
C
110
−C
11th
)/2)*
f
(
V
j1
)+
C
11th
*(
V
j1
−Vcgs
).
Note that the voltage between the drain and source, V
ds
, is related to the two voltages V
gs
and V
gd
described above by the relation:
V
ds
=V
gs
−V
gd
With such model, prediction of critical large signal parameters, namely: Output power, PAE, drain current, harmonic power and 3rd order Inter-Modulation Distortion (IMD), are provided with improved accuracy.
In accordance with another aspect of the invention, a method for determining large signal model values for a transistor includes obtaining device parameters of the transistor. The obtained device parameters are used to establish small signal model parameters in accordance with a small signal model of the transistor, such parameters including a gate-source capacitance C
gs
and a gate-drain capacitance C
dg
. Curve fitting is applied to C
gs
and C
dg
to establish large signal gate charge fitting parameters. The established large signal gate charge fitting parameters are used to establish a gate-source charge Q
gs
and a gate-drain charge Q
gd
as large signal model values for the transistor.
With such method, a more accurate modeling of transistors can be achieved.
In accordance with another aspect of the invention, a computer program product, residing on a computer readable medium, is provided including instructions for causing a computer to obtain measure the s-parameters of a transistor. The program includes instructions to cause the computer to determine small signal device parameters in accordance with a small signal model by curve fitting the measured s-parameters. One of such small signal parameters is a gate-source capacitance C
gs
which is a function of a gate-source voltage V
gs
and a drain-source voltage V
ds
, and another one of such small signal parameters being a drain-gate capacitance C
ds
which is a function of V
gs
and V
ds
. The program further includes instructions to cause the computer to determine gate charge fitting parameters, in accordance with a curve fitting operation, from C
gs
and C
ds
to establish a large signal gate-source charge Q
gs
and a large signal gate-drain charge Q
gd
.
With such an arrangement, computer modeling of transistors to achieve more accurate expected performance is achievable, which can assist in transistor design.
In accordance with another aspect of the invention, a computer program product, residing on a computer readable medium, includes instructions for causing a computer to obtain device parameters of the transistor. The program can use the obtained device parameters to establish small signal model parameters in accordance with a small signal model of the transistor, such parameters including a gate-source capacitance C
gs
and a gate-drain capacitance C
dg
. The program can apply curve fitting to C
gs
and C
dg
to establish large signal gate charge fitting parameters. The program can use the establishe
Mallavarpu Raghuveer
Teeter Douglas A.
Daly, Crowley & Mofford LLP
Raytheon Company
Sergent Douglas W.
Teska Kevin J.
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