Large scale integrated circuit and at speed test method thereof

Details Large scale integrated circuit and at speed test method thereof Large scale integrated circuit and at speed test method thereof

2007-02-06

2007-02-06

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S201000, C711S113000, C711S118000

Reexamination Certificate

active

11096137

ABSTRACT:
Disclosed are an apparatus and a method that at-speed-test a data cache included in a semiconductor integrated circuit by means of an on-chip memory having a size smaller than that of the data cache. A data cache has a first data storage area. An on-chip memory has a second data storage area smaller than the first data storage area, and stores test data. A address decoder decodes addresses so that the first data storage area is mapped to the second data storage area when an access for the test data stored in the on-chip memory is required.

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