Large scale IC personalization method employing air dielectric s

Details Large scale IC personalization method employing air dielectric s Large scale IC personalization method employing air dielectric s

1994-04-11

1996-06-25

Brown, Peter Toby

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257760, 257776, H01L 23528, H01L 23535

Patent

active

055302904

ABSTRACT:
Fabrication methods for forming a network of walls concurrently with the formation of studs for interconnecting plural device layers of a large scale integrated circuit device permits aggressive reduction of the average dielectric constant of air dielectric structures. Wall sections may be positioned to laterally support high aspect ratio connecting studs with a network of open or closed polygons. Wall patterns may also be open from layer to layer to allow formation of large scale air dielectric structures over a plurality of layers in a single material removal step. A wide range of shear strengths and reductions of average dielectric constant can be achieved even within a single device layer of a large scale integrated circuit and exploited to meet circuit design and device fabrication process requirements.

REFERENCES:
patent: 3890636 (1975-06-01), Harada et al.
patent: 4924289 (1990-05-01), Matsuoka
patent: 5034799 (1991-07-01), Tomita et al.
patent: 5095352 (1992-03-01), Noda et al.
patent: 5372969 (1994-12-01), Moslehi
Translation of Japan Kokai Publication #01-318248 to Tsuchiya et al., Dec. 1989, 24 pages.

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