Large dynamic range, low-leakage vertical color pixel sensor

Details Large dynamic range, low-leakage vertical color pixel sensor Large dynamic range, low-leakage vertical color pixel sensor

2005-11-15

2005-11-15

Pyo, Kevin (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controlled circuit

C250S214100, C257S291000, C348S308000

Reexamination Certificate

active

06965102

ABSTRACT:
A low-leakage, high-dynamic range active pixel sensor is formed on a p-type semiconductor substrate. A photodiode cathode n-type region is disposed within the semiconductor substrate forming a pn junction with the semiconductor substrate. An n-well is disposed in the semiconductor substrate and in electrical contact with the photodiode cathode n-type region. An annular p-well in the semiconductor substrate is disposed around and spaced apart from the n-well. An annular polysilicon gate region forming a gate for a reset transistor is disposed over a thick gate dielectric on the surface of the semiconductor substrate. An annular n-type region is disposed within and inward from an inner periphery of the annular p-well and has inner edges substantially aligned with an outer periphery of the annular polysilicon gate region. The annular n-type region forms a drain for the reset transistor. A surface n-type region is disposed in the n-well at the surface of the semiconductor substrate. The surface n-type region has outer edges substantially aligned with an inner periphery of the annular polysilicon gate region and forms a drain for the reset transistor. A thick gate dielectric sense transistor has a gate coupled to the surface n-type region, a drain coupled to a drain supply potential, and a source. An output transistor has a drain coupled to the source of the sense transistor, a gate coupled to a row-select line, and a source coupled to a column output line. Sources, drains, and gates of the transistors may be silicided.

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patent: 6639261 (2003-10-01), Rhodes
Richard B. Merrill, “Vertical Color Filter Derector Group And Array”, 36 pp. Specification. 19 pp. Claims, 2 pp. Abstract, 12 Drawing Sheets, U.S. Appl. No. 09/884,863, filed Jun. 18, 2001.

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