Large-capacity content addressable memory with sorted insertion

Details Large-capacity content addressable memory with sorted insertion Large-capacity content addressable memory with sorted insertion

2000-10-16

2001-06-26

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S189070, C365S230030

Reexamination Certificate

active

06252790

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a content addressable memory.
The present invention improves upon the following prior art:
1. U.S. Pat. No. 3,648,254 granted to W. F. Beausoleil on Mar. 7, 1972 discloses a content addressable memory (CAM) using less than one comparator per cell (shared comparators).
2. U.S. Pat. No. 4,145,737 granted to S. M. Lamb et al. on Mar. 20, 1979 discloses a CAM using shared comparators, wherein only a portion of the CAM storage is used for any given access.
3. U.S. Pat. No. 4,357,686 granted to J. H. Scheuneman on Nov. 2, 1982 discloses a dynamic memory (DRAM) with automatic refresh.
4. U.S. Pat. No. 4,622,653 granted to D. J. McElroy on Nov. 11, 1986 discloses a CAM using shared comparators with DRAM, wherein each row of the DRAM is read in turn during a search to find possible matches.
5. U.S. Pat. No. 4,627,024 granted to B. H. Whalen et al. on Dec. 2, 1986 discloses a content window addressable memory utilizing magnitude comparators rather than equality comparators.
6. U.S. Pat. No. 4,794,559 granted to A. J. Greenberger on Dec. 27, 1988 discloses a ternary CAM using shared comparators with DRAM.
7. U.S. Pat. No. 4,845,668 granted to J. Sano et al. on Jul. 4, 1989 discloses a variable-length content CAM.
8. U.S. Pat. No. 4,914,630 granted to K. Fujishima et al. on Apr. 3, 1990 discloses a DRAM with automatic refresh, wherein the memory is divided into banks and the inactive bank is refreshed.
9. U.S. Pat. No. 5,561,429 granted to M. Halberstam et al. on Oct. 1, 1996 discloses a content window addressable memory utilizing magnitude comparators rather than equality comparators, wherein the input and comparison words are split bit-wise into slices of more than one bit each and the comparators used for comparisons involving more than one slice.
10. U.S. Pat. No. 5,875,143 granted to J. Ben-Zvi on Feb. 23, 1999 discloses a DRAM with selective automatic refresh, wherein unused rows of the DRAM are not refreshed.
11. U.S. Pat. No. 6,061,262 granted to K. J. Schultz et al. on May 9, 2000 discloses a CAM using shared comparators, wherein the memory is segmented into a small number of blocks, and each block is read in turn during a search to find possible matches, using an internal clocking scheme.
The existing art, taken together, is capable of simultaneously achieving one or two of the goals of high speed, low power consumption, low cost and large capacity. It is the object of the invention to provide a content addressable memory architecture which can simultaneously reduce the cost and power consumption and increase the speed and capacity of content addressable memory beyond that which is currently available.
BRIEF SUMMARY OF THE INVENTION
An improvement on the prior art is achieved through a novel design which is capable of simultaneously supporting both of the following:
1. Reduced transistor count and higher capacity through use of dynamic memory cells without restriction as to cell array geometry; reduced numbers of comparators; and simple control mechanisms; and
2. Reduced power consumption and higher speed through examination and comparison of only a subset of content values to the comparand.
This design accomplishes these goals through the arrangement and indexing of data in the main content addressable memory to allow only a portion of the main memory to be examined for any given search. The additional circuitry required may be integrated into the control circuitry of the main memory.
This invention does not interfere with the adoption of a standard interface to the content addressable memory like those used in existing commercial non-dynamic content addressable memories.


REFERENCES:
patent: 4627024 (1986-12-01), Whalen et al.
patent: 4794559 (1988-12-01), Greenberger
patent: 5319589 (1994-06-01), Yamagata et al.
patent: 5388066 (1995-02-01), Hamamoto et al.
patent: 5438535 (1995-08-01), Lattibeaudiere
patent: 5870324 (1999-02-01), Helwig et al.
patent: 6061262 (2000-05-01), Schultz et al.
patent: 6081441 (2000-06-01), Ikeda
patent: 6169685 (2001-01-01), Gandini et al.

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