Radiation imagery chemistry: process – composition – or product th – Radiation modifying product or process of making – Radiation mask
Reexamination Certificate
2002-08-08
2004-12-28
Letscher, Geraldine (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Radiation modifying product or process of making
Radiation mask
C430S323000, C430S324000, C378S034000, C378S035000, C250S492210, C250S492220, C250S492230
Reexamination Certificate
active
06835508
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a large-area membrane mask for lithography methods with short-wave radiation, in particular for ion projection lithography, and to a method for fabricating such a membrane mask.
In semiconductor technology, nowadays the silicon wafers are patterned almost without exception by using the lithographic technique, in which first a resist pattern is produced on the wafer in a radiation-sensitive resist layer. This pattern then serves as a mask during a subsequent process step, e.g. an etching. Afterward, the resist mask is removed again. The resist pattern itself is likewise fabricated using a mask that is suitable for the respective exposure method. For this, conventional photolithography uses chromium masks (reticles) which include a glass plate as a carrier and a thin patterned chromium layer. Masks for X-ray lithography only allow mask carrier thicknesses in the micrometers range, however, even when weakly absorbing materials such as silicon are used. This is realized by membrane masks including a central active region, in which they are thinned toward the membrane, and a supporting edge (carrying ring) in the original thickness of the silicon substrate. A geometrically patterned absorber layer is fitted on the membrane layer in the case of X-ray masks.
Electron and ion lithography often use membrane masks in which the mask openings are produced in the membrane layer rather than on it. The membrane layer, which has a thickness in the micrometers range, contains mask openings or holes corresponding to the figures or patterns that will be produced lithographically. Consequently, such so-called perforated masks (stencil masks) are mechanically comparatively unstable structures, as in the case of all membrane masks.
For electron and ion projection lithography and recent versions of X-ray lithography, it is necessary to fabricate membrane masks with thicknesses in the micrometers range and with membrane areas having a size of up to more than 100 square centimeters. The membrane mask produced by the method according to the invention can generally be employed for lithography methods using charged particles and using photons. One exemplary use is in 13 nm lithography (so-called EUV beams). Another possible use is for masking with respect to neutral particles (atom lithography) and in all applications with a vapor deposition mask. Membrane masks as a product of a method according to the present invention can also generally be used for sensors.
Proceeding from silicon wafers as a typical substrate material, two different technological process variants have been followed heretofore for fabricating the membrane masks. They differ in principle with respect to whether the process steps for mask patterning, that is to say for perforation, are effected before (wafer flow process) or after (membrane flow process) the membrane etching, that is to say the removal of the wafer except for the remaining carrying ring.
In the so-called wafer flow process, as is presented, for example, in International Publication WO 99/49365, first the mask structures are produced on a compact silicon wafer and the membrane (area) is fabricated by etching the rear side of the substrate at the end of the process. This process variant makes it possible, on the one hand, to carry out the patterning processes for the mask structures on stable wafers whose processing can be better controlled. On the other hand, in this variant, very stringent requirements are also made of the membrane etching process, since the patterned membrane side must be absolutely securely protected against an etching attack. A boron doping of the membrane layer has conventionally been provided as an etching stop technique, as a result of which, however, conditions that are not defined exactly enough often result.
Therefore, SOI (Silicon-On-Insulator) substrates have also recently been used as is described in International Publication WO 99/49365. In this case, the buried oxide layer in the SOI wafer serves as a defined etching stop and the doping of the membrane layer can be chosen as desired according to other standpoints. Proceeding from a semiconductor/insulator/semiconductor carrier layer substrate, the future structure of the membrane is transferred into the topmost semiconductor layer; that is to say, into the future membrane layer. In a further step, the semiconductor carrier layer is removed from the underside except for an outer ring. Finally, in the central region, the uncovered insulator layer is also removed, with the result that the semiconductor layer bearing on the carrying ring with its uncovered central region clamped by the carrying ring represents the patterned membrane area.
In the future a positional accuracy in the region of a few nanometers will be demanded on the position of the structures that are introduced into the membrane and that are crucial for the function of the mask. In this case, depending on the desired inherent stress of the membrane layer, it is necessary first to take account of a more or less pronounced homogeneous displacement of the mask structures with respect to the original position, which, however, can be compensated for by precorrection. What are significantly more problematic are process- and storage-dictated distortions which, on account of the size of the membrane area (diameter typically 126 millimeters or more) and the low rigidity of the mask, greatly influence the positioning accuracy.
Stresses that can lead to distortions occur particularly in connection with SOI substrates. This is because of various reasons dictated by their construction or fabrication process. By way of example, the fabrication of buried oxide layers using wafer bonding is often accompanied, in practice, by mechanical irregularities which are manifested in inhomogeneous stresses in the upper, thin semiconductor layer.
The aforementioned carrying ring made of membrane material (typically silicon) has been used heretofore for stabilizing the membrane area. The carrying ring concentrically surrounds the membrane area and has a significantly larger thickness than the membrane. This mask geometry has usually been realized with an SOI wafer whose thickness on the membrane area has been reduced to a few micrometers by etching methods. The stabilization ring retains the original wafer thickness of a few hundred micrometers. Despite this stabilization, the rigidity of the overall system is not high enough to reduce the distortions that occur to the demanded order of magnitude that is indispensable for future use.
U.S. Pat. No. 6,214,498 B1 discloses a double-story membrane mask, which is constructed from two perforated membrane layers and the associated carrying rings, and a method for fabricating it. The starting point is the problem that the energy of the high-energy particles which is absorbed in the mask during the exposure operation leads to a thermal expansion, as a result of which a mask warpage occurs that can lead to unacceptable distortions during the imaging of the mask structures. In order to eliminate these thermal distortions triggered by the exposure itself, it is proposed to place two essentially mirror-symmetrical masks one on top of the other and to provide, in the region of the carrying rings, an intermediate piece which, on the one hand, mechanically connects the two masks but, on the other hand, thermally insulates them from one another. As a result, the thermal energy is absorbed in the upper mask near the radiation. The mask warpage of which does not influence the imaging, however, since its openings are somewhat larger than those of the lower mask, in which no mask warpage occurs on account of its shielding and insulation.
This known double mask is fabricated by patterning the two masks including the intermediate piece one beside the other on a conventional silicon wafer, which is subsequently divided into the two masks. The two masks are then fixed to one another in a mirror-inverted manner by using a conductive layer.
SUMMARY OF THE
Butschke Jörg
Ehrmann Albrecht
Haugeneder Ernst
Kamm Frank-Michael
Letzkus Florian
Greenberg Laurence A.
Infineon - Technologies AG
Letscher Geraldine
Locher Ralph E.
Stemer Werner H.
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