Large area electronic device with high and low resolution...

Etching a substrate: processes – Forming or treating thermal ink jet article

Reexamination Certificate

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C438S745000, C430S311000

Reexamination Certificate

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07125495

ABSTRACT:
Two different processing techniques are utilized to respectively form high resolution features and low resolution features in a critical layer of an electronic device, and in particular a large area electronic device. High resolution features are formed by soft lithography, and low resolution features are formed by jet-printing or using a jet-printed etch mask. Jet-printing is also used to stitch misaligned structures. Alignment marks are generated with the features to coordinate the various processing steps and to automatically control the stitching process. Thin-film transistors are formed by generating gate structures using a first jet-printed etch mask, forming source/drain electrodes using soft lithography, forming interconnect structures using a second jet-printed etch mask, and then depositing semiconductor material over the source/drain electrodes. Redundant structures are formed to further improve tolerance to misalignment, with non-optimally positioned structures removed (etched) during formation of the low resolution interconnect structures.

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patent: 6413790 (2002-07-01), Duthaler et al.
patent: 6655286 (2003-12-01), Rogers
patent: 2004/0219246 (2004-11-01), Jeans
Michael D. Austin and Stephen Y. Chou “Fabrication of 70nm channel length polymer organic thin-film transistors using nanoimprint lithography”, Applied Physics Letters, vol. 81, No. 23, Dec. 2, 2002.

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