Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Layout editor
Reexamination Certificate
2008-05-16
2011-10-11
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Layout editor
Reexamination Certificate
active
08037448
ABSTRACT:
During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to one or more templates used to generate shells for the specification of a final semiconductor product. Data must be correct and compatible with other data before it can be used within the template engine and the generated shells; indeed the template engine cooperates with a plurality of rules and directives to verify the correctness of the data. The template engine may generate one or more of the following shells: an RTL shell, a documentation shell, a timing analysis shell, a synthesis shell, a manufacturing test shell, and/or a floorplan shell.
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Nordman John Emery
Youngman Todd Jason
Bowers Brandon
Brush David D.
Chiang Jack
LSI Corporation
Westman Champlin & Kelly P.A.
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