Land pattern configuration

Details Land pattern configuration Land pattern configuration

2006-04-04

2006-04-04

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

C439S060000

Reexamination Certificate

active

07023081

ABSTRACT:
The pin pitches on the respective edges of a plurality of selectively mounted semiconductor devices match one another, and the distances between the edges differ from one another. Shared lands are arranged so as to correspond to contact pins disposed on one edge of the respective semiconductor devices. Accordingly, selectively mounting a plurality of types of semiconductor devices onto a printed circuit board is achieved while saving space.

REFERENCES:
patent: 5834832 (1998-11-01), Kweon et al.
patent: 5966020 (1999-10-01), Rampone et al.
patent: 6347950 (2002-02-01), Yokoyama et al.
patent: 6403895 (2002-06-01), Sota
patent: 6-140814 (1994-05-01), None
patent: 6-188656 (1994-07-01), None

Affiliated with

Also associated with

Rating

Land pattern configuration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Land pattern configuration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Land pattern configuration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3579103